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| 型號： | TMS320F206PZA |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 23/57頁 |
| 文件大?。?/td> | 793K |
| 代理商： | TMS320F206PZA |
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TMS320F206
DIGITAL SIGNAL PROCESSOR
SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998
23
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
software-controlled wait-state generator (continued)
Table 10. Wait-State(s) Programming
ISWS, DSWS, PSUWS, OR PSLWS BITS
WAIT STATES FOR PROGRAM, DATA, OR I/O
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
Table 11. Wait-State Generator Control Register (WSGR)
BITS
NAME
DESCRIPTION
2–0
PSLWS
External program space wait states (lower). PSLWS determines that between 0 to 7 wait states are applied to
all reads and writes to off-chip lower program space address (0h–7FFFh). The memory cycle can be further
extended by using the READY signal. The READY signal does not override the wait states generated by PSWS.
These bits are set to 1 (active) by reset (RS).
5–3
PSUWS
External program space wait states (upper). PSUWS determines that between 0 to 7 wait states are applied to
all reads and writes to off-chip upper program space address (8000h–0FFFFh). The memory cycle can be further
extended by using the READY signal. The READY signal does not override the wait states generated by PSWS.
These bits are set to 1 (active) by reset (RS).
8–6
DSWS
External data space wait states. DSWS determines that between 0 to 7 wait states are applied to all reads and
writes to off-chip data space. The memory cycle can be further extended by using the READY signal. The READY
signal does not override the wait states generated by DSWS. These bits are set to 1 (active) by reset (RS).
11–9
ISWS
External input /output space wait state. DSWS determines that between 0 to 7 wait states are applied to all reads
and writes to off-chip I/O space. The memory cycle can be further extended by using the READY signal. The
READY signal does not override the wait states generated by ISWS. These bits are set to 1 (active) by reset (RS).
15–12
X
Don’t care
timer
The TMS320F206 includes a 20-bit timer, implemented with a 16-bit main counter (TIM), and a 4-bit prescaler
counter (PSC). The count values are written into the 16-bit period register (PRD), and the 4-bit timer divide-down
register (TDDR). The TIM and the PRD are 16-bit registers mapped to I/O space, while the PSC and the TDDR
are 4-bit fields of the timer control register (TCR). The TCR is an I/O mapped register which also includes other
control bits for the timer (see Table 8).
When the timer is started, the TIM is loaded with the contents of PRD, and the PSC is loaded with the contents
of the TDDR. The PSC is decremented by one at each CLKOUT1 cycle. On the CLKOUT1 cycle after the PSC
decrements to zero, the PSC is reloaded with the contents of TDDR, and the TIM is decremented by one. That
is, every (TDDR+1) CLKOUT1 cycles, the TIM is decremented by one. When the TIM decrements to zero, it
is reloaded with the contents of the PRD on the following CLKOUT1 cycle, and a new timer interval begins.
Therefore, the timer interrupt rate is defined as follows: CLKOUT1 frequency/[(TDDR+1) (PRD+1)].
The timer can be used to generate periodic CPU interrupts based on CLKOUT1. Each time the TIM decrements
to zero, a timer interrupt (TINT) is generated, and a pulse equal to the duration of a CLKOUT1 cycle is generated
on the TOUT pin. The timer provides a convenient means of performing periodic I/O, context switching , or other
functions.
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