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參數(shù)資料
| 型號： | TMS320F206PZA |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 22/57頁 |
| 文件大?。?/td> | 793K |
| 代理商： | TMS320F206PZA |
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TMS320F206
DIGITAL SIGNAL PROCESSOR
SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998
22
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
reset
The TMS320F206 utilizes an active-low reset (RS) input.
A minimum pulse duration of six cycles ensures that an asynchronous reset signal resets the device properly.
The TMS320F206 fetches its first instruction approximately sixteen cycles after the rising edge of RS.
The reset action halts all operations whether they are completed or not; therefore, the state of the system and
its data cannot be maintained through the reset operation. For example, if the device is writing to an external
resource when the reset is initiated, the write is aborted; this may corrupt the contents or configuration of system
resources. Therefore, it is necessary to reinitialize the system after a reset.
power-down modes
The ’F206 implements a power-down mode in which the ’F206 core enters a dormant state and dissipates less
power. The power-down mode is invoked by executing an IDLE instruction. While the device is in power-down
mode, the on-chip peripherals continue to operate.
While the ’F206 is in a power-down mode, all of its internal contents are maintained; this allows operation to
continue unaltered when the power-down mode is terminated. All CPU activities are halted when the IDLE
instruction is executed, but the CLKOUT1 pin remains active depending on the status of ICR register. The
peripheral circuits continue to operate, allowing peripherals such as serial ports and timers to take the CPU out
of its powered-down state. The power-down mode, when initiated by an IDLE instruction, is terminated upon
receipt of an interrupt.
software-controlled wait-state generator
Due to the fast cycle time of the TMS320F206 devices, it is often necessary to operate with wait states to
interface with external logic or memory. For many systems, one wait state is adequate.
The software wait-state generator can be programmed to generate between 0 and 7 wait states for a given
space. Software wait states are configured by way of the wait-state generator register (WSGR). The WSGR
includes four 3-bit fields to configure wait states for the following external memory spaces: data space (DSWS),
upper program space (PSUWS), lower program space (PSLWS), and I/O space (ISWS). The wait-state
generator enables wait states for a given memory space based on the value of the corresponding three bits,
regardless of the condition of the READY signal. The READY signal can be used to generate additional wait
states. All bits of the WSGR are set to 1 at reset so that the device can operate from slow memory from reset.
The WSGR register (shown in Table 9, Table 10 and Table 11) resides at I/O port 0xFFFCh.
Table 9. Wait-State Generator Control Register (WSGR)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
ISWS
DSWS
PSUWS
PSLWS
0
R/W–111
R/W–111
R/W–111
R/W–111
LEGEND:
0 = Always read as zeros, R = Read Access, W= Write Access, – n = Value after reset
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