參數(shù)資料
型號: TMS320F206PZA
元件分類: 數(shù)字信號處理
英文描述: 16-Bit Digital Signal Processor
中文描述: 16位數(shù)字信號處理器
文件頁數(shù): 17/57頁
文件大小: 793K
代理商: TMS320F206PZA
TMS320F206
DIGITAL SIGNAL PROCESSOR
SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998
17
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
memory (continued)
Table 7. TMS320F206 Memory Map
DESCRIPTION OF MEMORY BLOCK
DATA MEMORY
ADDRESS
PROG MEMORY
ADDRESS
MP/MC
DON
PON
CNF
BIT
256 x 16 word dual-access RAM (DARAM)
(B0)
0x100 – 0x1FFh
0x200 – 0x2FFh
x
x
x
0
256 x 16 word DARAM (B0)
0xFE00 – 0xFEFFh
0xFF00 – 0xFFFFh
x
x
x
1
256 x 16 word DARAM (B1)
0x300 – 0x3FFh
0x400 – 0x4FFh
x
x
x
x
32 x 16 word DARAM (B2)
32K x 16 word program flash memory§
0x60 – 0x7Fh
x
x
x
x
0x0000 – 0x7FFFh
0
x
x
x
32K x 16 word external program memory
0x0000 – 0x7FFFh
1
x
x
x
32K x 16 word external program memory
0x8000h – 0xFFFFh
x
x
0
0
External
0x8000h – 0xFDFFh
x
x
0
1
4K x 16 word data single-access RAM
(SARAM)
0x800 – 0x17FFh
x
1
x
x
4K x 16 word program SARAM
4K x 16 word program and data SARAM
0x8000 – 0x8FFFh
x
x
1
x
0x800 – 0x17FFh
0x8000 – 0x8FFFh
x
1
1
x
4K x 16 word SARAM
Denotes don’t care condition
The DARAM blocks B0 and B1 are mapped to dual address ranges as shown in the table. For more details on this mapping, see the last paragraph
in the memory section.
§The 32K x 16 flash memory consists of two 16K x 16 flash modules designated by FLASH0 and FLASH1.
The single SARAM (4K) block is accessible from both data and program memory space.
not available
not available
x
0
0
x
flash memory (EEPROM)
Flash EEPROM provides an attractive alternative to masked program ROM. Like ROM, flash is a nonvolatile
memory type; however, it has the advantage of “in-target” reprogrammability. The TMS320F206 incorporates
two 16K
16-bit flash EEPROM modules which provide a contiguous 32K
This type of memory expands the capabilities of the TMS320F206 in the areas of prototyping, early field-testing,
and single-chip applications.
16-bit array in program space.
Unlike most discrete flash memory, the ’F206 flash does not require a dedicated state machine, because the
algorithms for programming and erasing the flash are executed by the DSP core. This enables several
advantages, including: reduced chip size and sophisticated, adaptive algorithms. For production programming,
the IEEE Standard 1149.1 (JTAG) scan port provides easy access to the on-chip RAM for downloading the
algorithms and flash code. Other key features of the flash include zero-wait-state access rate and single 5-V
power supply.
An erased bit in the TMS320F206 flash is read as a logic 1, and a programmed bit is read as a logic 0. The flash
requires a block-erase of each of the two 16K modules; however, any combination of bits can be programmed.
The following four algorithms are required for flash operations: clear, erase, flash-write, and program. For an
explanation of these algorithms and a complete description of the flash EEPROM, refer to the
TMS320F20x/F24x DSPs Embedded Flash Memory Technical Reference(literature number SPRU282)
available during the 2nd quarter of 1998.
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