參數(shù)資料
型號(hào)： TMPR4955
廠商： Toshiba Corporation
英文描述： 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡(jiǎn)指令集系統(tǒng)計(jì)算機(jī)微處理器)
中文描述： 64位RISC（精簡(jiǎn)指令集計(jì)算機(jī)）微處理器（64位精簡(jiǎn)指令集系統(tǒng)計(jì)算機(jī)微處理器）
文件頁(yè)數(shù)： 47/60頁(yè)
文件大?。?/td> 244K
代理商： TMPR4955
TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
47
5.11 System Interface Addresses
System interface addresses in the 64-bit bus mode are complete 36-bit physical addresses. They are sent
to the lower 36 bits (bits 35 – 0) of the SysAD bus during the address cycle. The remaining bits of the
SysAD bus are not used by the address cycle.
System interface addresses in the 32-bit bus mode are complete 32-bit physical addresses. They are sent
to the lower 32 bits of the SysAD bus during the address cycle.
5.11.1 Addressing rules in the 64-bit bus mode
Addresses that are to be used in double word, partial double word, word or partial word transactions are
arranged to match the size of the data element. The following rules are used by this system.
Target addresses of the block request are aligned to the double word boundaries. In other words,
the lower 3 bits of the address become “0.”
For double word requests, the lower 3 bits of the address are set to “0.”
Word requests set the lower 2 bits of the address to “0.”
Half word requests set the least significant bit of the address to “0.”
Byte requests, 3-byte requests, 5-byte requests, 6-byte requests and 7-byte requests use the byte
address.
5.11.2 Addressing rules in the 32-bit bus mode
Addresses that are to be used in word or partial word transactions are arranged to match the size of the
data element. The following rules are used by this system.
Target addresses of the block request are aligned to the word boundaries. In other words, the
lower 2 bits of the address become “0.”
Word requests set the lower 2 bits of the address to “0.”
Half-word requests set the least significant bit of the address to “0.”
Byte requests and 3-byte requests use the byte address.
5.12
Mode Register of System Interface ( G2Sconfig )
The Mode Register of System Interface ( G2Sconfig ) is a write only register. This register is only Word-
Access.
Address
Field
Description
0xF_FF10_0000
G2Sconfig
Mode Register of System Interface
Table 12-1 G2Sconfig
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參數(shù)描述
TMPR4955A 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:64-Bit TX System RISC TX49 Family
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TMPR4955AF-200 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|64-BIT|CMOS|QFP|160PIN|PLASTIC
TMPR4955B 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:64-Bit TX System RISC TX49 Family
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