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| 型號： | TMPR4955 |
| 廠商： | Toshiba Corporation |
| 英文描述： | 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計算機微處理器) |
| 中文描述： | 64位RISC（精簡指令集計算機）微處理器（64位精簡指令集系統(tǒng)計算機微處理器） |
| 文件頁數(shù)： | 16/60頁 |
| 文件大?。?/td> | 244K |
| 代理商： | TMPR4955 |
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TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
16
into the slave state. Shifts from the master state to the slave state are arbitrated by the processor using the
system interface handshake signals ExtRqst* and Release.* This shift is performed as follows below.
1)
The external agent sends notification that it would like to issue an external request by asserting the
ExtRqst* signal.
2)
The processor releases the system interface and changes its state from the master state to the slave
state by asserting the Release* signal for 1 cycle.
3)
The system interface returns to the master state when issuing of the external request is complete.
5.4.4 Shifting to the slave state on its own
Shifting to the slave state on its own means that the shift from the master state to the slave state is started
by the processor when the processor read request is still on hold. The Release* signal is automatically
asserted after the read transaction. Self-invoked shifting to the slave state occurs either during the issue
cycle of the read request or several cycles after that.
After shifting to the slave state on its own, the processor returns to the master state at the end of the next
external request. This is made possible by a read request or other type of external request.
The SysAd bus and SysCmd bus drives must start after the external agent confirms that the processor
autonomously shifted to the slave state. While the system interface is in the slave state, the external agent
can start making external requests without requesting access to the system interface (without asserting the
ExtRqst* signal).
The system interface returns to the master state when the external request ends.
If a processor read request is on hold after a read request is issued, the processor automatically changes
the system interface into the slave state even if the system interface access necessary for the system agent
to issue the external request has not been requested. By shifting to the slave state in this manner, the
external agent becomes able to return read response data.
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| TMPR4956F | 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計算機微處理器) |
| TMPZ84C015AF | C-MOS 8-BIT MICROPROCCESSOR |
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| TMS2716 | 2048-WORD BY 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIES |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMPR4955A | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:64-Bit TX System RISC TX49 Family |
| TMPR4955AF | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:64-Bit TX System RISC TX49 Family |
| TMPR4955AF-167 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| TMPR4955AF-200 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|64-BIT|CMOS|QFP|160PIN|PLASTIC |
| TMPR4955B | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:64-Bit TX System RISC TX49 Family |
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