- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385939 > TMPR4955 (Toshiba Corporation) 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計(jì)算機(jī)微處理器) PDF資料下載
參數(shù)資料
| 型號： | TMPR4955 |
| 廠商： | Toshiba Corporation |
| 英文描述： | 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計(jì)算機(jī)微處理器) |
| 中文描述： | 64位RISC（精簡指令集計(jì)算機(jī)）微處理器（64位精簡指令集系統(tǒng)計(jì)算機(jī)微處理器） |
| 文件頁數(shù)： | 35/60頁 |
| 文件大?。?/td> | 244K |
| 代理商： | TMPR4955 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁當(dāng)前第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
35
data when it receives an external read request.
5.7.9 External null request protocol
The processor only supports one external null request. The system interface release external null request
returns the system interface from the slave state to the master state. This request does not affect any other
processors.
The only processing the external null request does is to have the processor return the system interface to
the master state.
Figure 7-9 illustrates the timing of the external null request, which consists of the following steps.
1.
The external agent requests use of the system interface by asserting ExtRqst*.
2.
The processor asserts Release*, then the system interface is released from the processor and goes into
the slave state.
3.
The external agent drives the system interface, sends the external null request command to the
SysCmd bus, then asserts the ValidIn* signal for 1 cycle.
4.
The SysAD bus is not available during the external null request address cycle (there are no valid data
in the bus).
5.
The null request ends when the address cycle is issued.
In the case of a system interface release null request, the external agent releases the SysCmd bus and
SysAD bus so the system interface can return to the master state. This protocol is the same for both the
32-bit and 64-bit bus modes.
Figure 7-9 System Interface Release External Null Request
Master
Clock
SysAD bus
Cycle
SysCmd bus
ValidOut*
ValidIn*
ExtRqst*
Release*
1
2
3
4
5
6
7
8
9
10
11
12
Unsd
4
SINull
5
3
Slave
Master
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMPR4956F | 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計(jì)算機(jī)微處理器) |
| TMPZ84C015AF | C-MOS 8-BIT MICROPROCCESSOR |
| TMPZ84C61AP-6 | TLCS-Z80 CGC : Z80 CLOCK GENERATOR/CONTROLLER |
| TMS2716 | 2048-WORD BY 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIES |
| TMS2716-30 | 2048-WORD BY 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIES |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMPR4955A | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:64-Bit TX System RISC TX49 Family |
| TMPR4955AF | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:64-Bit TX System RISC TX49 Family |
| TMPR4955AF-167 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| TMPR4955AF-200 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|64-BIT|CMOS|QFP|160PIN|PLASTIC |
| TMPR4955B | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:64-Bit TX System RISC TX49 Family |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。