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參數(shù)資料
| 型號： | TMPR4955 |
| 廠商： | Toshiba Corporation |
| 英文描述： | 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計算機微處理器) |
| 中文描述： | 64位RISC（精簡指令集計算機）微處理器（64位精簡指令集系統(tǒng)計算機微處理器） |
| 文件頁數(shù)： | 14/60頁 |
| 文件大?。?/td> | 244K |
| 代理商： | TMPR4955 |
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TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
14
The TX4956 repeats the request address cycle until the conditions of the valid issue cycle are met. If the
processor request is a data transmission, then data transmission starts at the point when the issue cycle is
complete. There is only one issue cycle no matter what the processor request is.
The TX4956 accepts external requests even while trying to issue processor requests. If the external agent
asserts ExtRqst*, the processor responds to the external agent by releasing the system interface and going
into the slave state. Rules relating to the issue cycle of processor requests are strictly applied in
determining the processor run operation as well. The TX4956 performs one of the following:
Complete issuing of processor requests before external requests are received.
Release the system interface and go into the slave mode without completing issuance of the
processor requests.
In the latter of the above situations, the TX4956 issues processor requests after external requests are
complete. Rules relating to issuing are also provided to processor requests.
5.3.4 Handshake signal
The processor uses the eight control signals explained below to manage the flow of requests.
RdRdy* and WrRdy* are used by the external agent to indicate that it is possible to receive new
read transactions (RdRdy*) or new write transactions (WrRdy*).
ExtRqst* and Release* are used to transfer SysAD bus and SysCmd bus control. ExtRqst* is
used by the external agent to indicate the necessity of controlling the interface. Release* is
asserted by the processor when transferring the system interface access privileges.
The TX4956 processor uses ValidOut* and the external agent ValidIn* signals to indicate the
valid command/data on the SysCmd/SysAD bus.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMPR4956F | 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計算機微處理器) |
| TMPZ84C015AF | C-MOS 8-BIT MICROPROCCESSOR |
| TMPZ84C61AP-6 | TLCS-Z80 CGC : Z80 CLOCK GENERATOR/CONTROLLER |
| TMS2716 | 2048-WORD BY 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIES |
| TMS2716-30 | 2048-WORD BY 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIES |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMPR4955A | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:64-Bit TX System RISC TX49 Family |
| TMPR4955AF | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:64-Bit TX System RISC TX49 Family |
| TMPR4955AF-167 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| TMPR4955AF-200 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|64-BIT|CMOS|QFP|160PIN|PLASTIC |
| TMPR4955B | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:64-Bit TX System RISC TX49 Family |
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