![](http://datasheet.mmic.net.cn/240000/5082-7623-BE200_datasheet_15638971/5082-7623-BE200_91.png)
P
1
9
SPI MASTER MODE TIMING PARAMETERS
SPI master mode timing information is listed in the following tables.
SPI master mode external timing parameters (clock phase = 0)
(see Figure 41)
NO.
SPI WHEN (SPIBRR + 1) IS EVEN
OR SPIBRR = 0 OR 2
SPI WHEN (SPIBRR + 1)
IS ODD AND SPIBRR > 3
MIN
MAX
MIN
1
t
c(SPC)M
Cycle time, SPICLK
4t
c(CO)
128t
c(CO)
5t
c(CO)
§
2
t
w(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 0)
0.5t
c(SPC)M
10
0.5t
c(SPC)M
0.5t
c(SPC)M
0.5t
c(CO)
10
t
w(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 1)
0.5t
c(SPC)M
10
0.5t
c(SPC)M
0.5t
c(SPC)M
0.5t
c(CO)
10
§
3
t
w(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 0)
0.5t
c(SPC)M
10
0.5t
c(SPC)M
0.5t
c(SPC)M
+0.5t
c(CO)
10
0.5t
t
w(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 1)
0.5t
c(SPC)M
10
0.5t
c(SPC)M
0.5t
c(SPC)M
+0.5t
c(CO)
10
0.5t
4
§
t
d(SPCH-SIMO)M
Delay time, SPICLK high to
SPISIMO valid (clock polarity = 0)
10
10
10
t
d(SPCL-SIMO)M
Delay time, SPICLK low to
SPISIMO valid (clock polarity = 1)
10
10
10
5
§
t
v(SPCL-SIMO)M
Valid time, SPISIMO data valid after
SPICLK low (clock polarity =0)
0.5t
c(SPC)M
10
0.5t
c(SPC)M
+0.5t
c(CO)
10
t
v(SPCH-SIMO)M
Valid time, SPISIMO data valid after
SPICLK high (clock polarity =1)
0.5t
c(SPC)M
10
0.5t
c(SPC)M
+0.5t
c(CO)
10
8
§
t
su(SOMI-SPCL)M
Setup time, SPISOMI before
SPICLK low (clock polarity = 0)
0
0
t
su(SOMI-SPCH)M
Setup time, SPISOMI before
SPICLK high (clock polarity = 1)
0
0
9
§
t
v(SPCL-SOMI)M
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 0)
0.25t
c(SPC)M
10
0.5t
c(SPC)M
0.5t
c(CO)
10
t
v(SPCH-SOMI)M
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 1)
0.25t
c(SPC)M
10
0.5t
c(SPC)M
0.5t
c(CO)
10
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
t
c
= system clock cycle time = 1/CLKOUT = t
c(CO)
§
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).