![](http://datasheet.mmic.net.cn/240000/5082-7623-BE200_datasheet_15638971/5082-7623-BE200_6.png)
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K
JULY 2000
REVISED AUGUST 2005
6
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
functional block diagram of the 2407A DSP controller
XTAL1/CLKIN
XTAL2
ADCIN00
ADCIN07
PLLV
CCA
PLLF2
PLLF
V
SSA
V
REFHI
V
REFLO
ADCIN08
ADCIN15
V
CCA
SCIRXD/IOPA1
SPISIMO/IOPC2
XINT2/ADCSOC/IOPD0
SCITXD/IOPA0
Port A(0
7) IOPA[0:7]
SPICLK/IOPC4
SPISTE/IOPC5
SPISOMI/IOPC3
Port E(0
7) IOPE[0:7]
Port F(0
6) IOPF[0:6]
TRST
Port C(0
7) IOPC[0:7]
Port D(0) IOPD[0]
Port B(0
7) IOPB[0:7]
TDO
TDI
TMS
CANRX/IOPC7
CANTX/IOPC6
EMU1
PDPINTB
TCK
EMU0
CAP5/QEP4/IOPF0
CAP6/IOPF1
CAP4/QEP3/IOPE7
PWM7/IOPE1
PWM8/IOPE2
PWM10/IOPE4
PWM9/IOPE3
PWM11/IOPE5
PWM12/IOPE6
T4PWM/T4CMP/IOPF3
TDIRB/IOPF4
TCLKINB/IOPF5
T3PWM/T3CMP/IOPF2
DARAM (B0)
256 Words
DARAM (B1)
256 Words
DARAM (B2)
32 Words
C2xx
DSP
Core
PLL Clock
10-Bit ADC
(With Twin
Autosequencer)
èèèèèèè
èèèèèèè
èèèèèèè
èèèèèèè
èèèèèèè
èèèèèèè
èèèèèèèèèèèèè
èèèèèèè
èèèèèèè
èèèèèèè
èèèèèèè
èèèèèèè
èèèèèèè
èèèèèèè
èèèèèèè
èèèèèèè
RS
CLKOUT/IOPE0
XINT1/IOPA2
BIO/IOPC1
MP/MC
TMS2
A0
A15
D0
D15
TP1
TP2
BOOT_EN/XF
V
DD
(3.3 V)
READY
STRB
R/W
RD
PS, DS, IS
VIS_OE
ENA_144
WE
CAP3/IOPA5
PWM1/IOPA6
PWM2/IOPA7
CAP1/QEP1/IOPA3
CAP2/QEP2/IOPA4
PDPINTA
PWM5/IOPB2
PWM6/IOPB3
PWM3/IOPB0
PWM4/IOPB1
T2PWM/T2CMP/IOPB5
T1PWM/T1CMP/IOPB4
TCLKINA/IOPB7
TDIRA/IOPB6
V
SS
V
CCP
(5V)
èèèèèèè
èèèèèèèèèèèèè
èèèèèèèèèèèèè
èèèèèèèèèèèèè
èèèèèèèèèèèèè
èèèèèèèèèèèèè
èèèèèèè
èèèèèèè
Flash/ROM
4K/12K/12K/4K)
External Memory
Event Manager A
3
×
Capture Input
6
×
Compare/PWM
Output
2
×
GP
Timers/PWM
SCI
Digital I/O
(Shared With
Other Pins)
CAN
JTAG Port
Event Manager B
3
×
Capture Input
Output
2
GP
Timers/PWM
èèè
èèè
èèè
Indicates optional modules
.
The memory size and peripheral selection of these modules change for different 240xA devices.
See Table 1 for device-specific details.
W/R / IOPC0