參數(shù)資料
型號： TLC320AD52C
廠商： Texas Instruments, Inc.
英文描述： Sigma-Delta Analog Interface Circuits With Master-Slave Function(帶主從功能的∑△模擬接口電路,高分辨率信號轉(zhuǎn)換)
中文描述： sigma - delta模擬接口電路的主從功能（帶主從功能的Σ△模擬接口電路，高分辨率信號轉(zhuǎn)換）
文件頁數(shù)： 18/59頁
文件大?。?/td> 306K
代理商： TLC320AD52C
2–4
2.1.4
The digital serial interface consists of the shift clock (SCLK), the frame-sync signal (FS), the ADC-channel
data output (DOUT), and the DAC-channel data input (DIN). During the primary frame synchronization
interval, SCLK clocks the ADC channel results out through DOUT and clocks 16-bit/(15+1)-bit DAC data
in through DIN.
Serial Interface
During the secondary frame-sync interval, SCLK clocks the register read data out through DOUT if the read
bit (DS13) is set to 1 and transfers control and device parameter in through DIN. The timing sequence is
shown in Figures 2–2 and 2–4.
2.1.5
Register Programming
All register programming occurs during secondary communications through DIN, and data are latched and
valid on the falling edge of SCLK during the frame-sync signal. If the default value for a particular register
is desired, that register does not need to be addressed during the secondary communications interval. The
no-op command (DS15 – DS8 all set to 0) addresses the pseudo-register (register 0), and no register
programming takes place during the communications.
In addition, each register can be read back through DOUT during secondary communications by setting the
read bit (DS13) to 1. When the register is in the read mode, no data can be written to the register during this
cycle. DS13 must be cleared to write to the register.
For example, if the contents of control register 1 is desired to be read out from DOUT, the following procedure
must be performed through DIN:
1.
Request secondary communication by setting either D0 = 1 (software request) or FC = high
(hardware request) during the primary communication interval.
2.
At the secondary communication interval (FS), send data in the following format in through DIN:
0
0
1
0
0
0
0
1
x
x
x
x
x
x
x
x
DS15
DS0
3.
Then the following data is read from DOUT, with the last 8 bits containing the register 1 data.
0
0
1
0
0
0
0
1
d
d
d
d
d
d
d
d
DS15
DS0
Figure 2–5 is a timing diagram of this procedure.
FS
DIN
P
DOUT
Low 8 Bits (DS0–DS7) are the
Content of Register 1
Register 1 Read
S
Figure 2–5. Register 1 Read Operation Timing Diagram
相關(guān)PDF資料
PDF描述
TLC320AD55C Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口)
TLC320AD56(中文) Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口)
TLC320AD56C Sigma-Delta Analog Interface Circuit
tlc320ad56c Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口電路)
TLC320AD57(中文) Sigma-Delta Analog Interface Circuit(Sigma-Delta立體聲音頻ADC)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLC320AD52CDW 制造商:TI 制造商全稱:Texas Instruments 功能描述:SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION
TLC320AD52CPT 功能描述:IC ANALOG INTERFACE W/MS 48-LQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:PCM 數(shù)據(jù)接口:PCM 音頻接口 分辨率（位）:15 b ADC / DAC 數(shù)量:1 / 1 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):- 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):- 電壓 - 電源，模擬:2.7 V ~ 3.3 V 電壓 - 電源，數(shù)字:2.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:80-VFBGA 供應(yīng)商設(shè)備封裝:80-BGA MICROSTAR JUNIOR（5x5） 包裝:帶卷 (TR) 其它名稱:296-21257-2
TLC320AD535 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC
TLC320AD535C 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC
TLC320AD535C-I 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC
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