參數(shù)資料
型號： TLC320AD52C
廠商： Texas Instruments, Inc.
英文描述： Sigma-Delta Analog Interface Circuits With Master-Slave Function(帶主從功能的∑△模擬接口電路,高分辨率信號轉(zhuǎn)換)
中文描述： sigma - delta模擬接口電路的主從功能（帶主從功能的Σ△模擬接口電路，高分辨率信號轉(zhuǎn)換）
文件頁數(shù)： 17/59頁
文件大小： 306K
代理商： TLC320AD52C
2–3
SCLK
FS
DIN
(16-Bit)
DIN
(15+1-Bit)
16 SCLKs
LSB
LSB
1
2
15
16
D15
d15
D14
d14
D1
d1
D0
d0=0
MSB
MSB
17
See Note
NOTE: d0 = 0 means no secondary communication request (software secondary communication request control —
paragraph 3.2)
Figure 2–3. Timing Sequence of DAC Channel (Primary Communication Only)
During secondary communication, the digital control and configuration data (together with the register
address), are clocked in through DIN. These 16-bits of data are used either to initialize the register, or to
read the register content through DOUT. If a register initialization is not required, a no-operation word (DS15
– DS8 are all set to 0) can be used. If DS13 is set to 1, the content of the control register, specified by
DS12–DS8, will be sent out through DOUT during the same secondary communication (see section 2.1.5).
The timing sequence is shown in figure 2–4.
Primary
FS
DIN (16-Bit)
(see Note A)
16 SCLKs
16-Bit DAC Data
16 SCLKs
Primary
Secondary
DIN
(15 +1-Bit)
15-Bit DAC Data
+ D0=1
(see Note B)
Register Read/Write
128 SCLKs
256 SCLKs
Register Read/Write
NOTES: A. FC has to be set high for a secondary communication request when 16–bit DAC data format is used
(paragraph 3.2).
B. D0 = 1 means secondary communication request (software secondary communication request control —
paragraph 3.2).
Figure 2–4. Timing Sequence of DAC Channel (Primary and Secondary Communication)
相關(guān)PDF資料
PDF描述
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TLC320AD56C Sigma-Delta Analog Interface Circuit
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