參數資料
型號: TLC320AD52C
廠商: Texas Instruments, Inc.
英文描述: Sigma-Delta Analog Interface Circuits With Master-Slave Function(帶主從功能的∑△模擬接口電路,高分辨率信號轉換)
中文描述: sigma - delta模擬接口電路的主從功能(帶主從功能的Σ△模擬接口電路,高分辨率信號轉換)
文件頁數: 13/59頁
文件大?。?/td> 306K
代理商: TLC320AD52C
1–7
1.7
There are seven control registers that are used as follows:
Register 0
The No-Op register. Addressing register 0 allows secondary communications requests
without altering any other register.
Register Functional Summary
Register 1
The Control 1 register. The data in this register controls:
Software reset
Software power down
Normal or auxiliary analog inputs enabling
Normal or auxiliary analog inputs monitoring
Selection of monitor amplifier output gain
Selection of digital loopback
Selection of16-bit or (15+1)-bit mode of DAC operation
Register 2
The Control 2 register. The data in this register:
Contains the output value of FLAG
Selects phone mode
Contains the output flag indicating a decimator FIR filter overflow
Selects either 16-bit mode or (15+1)-bit mode of ADC operation
Enables analog loopback
Register 3
The Control 3 register. The data in this register:
Sets the number of SCLK delays between FS and FSD
Informs the master device of how many slaves are connected in the chain
Register 4
The Control 4 register. The data in this register:
Selects the amplifier gain for the input and output amplifiers
Sets the sample rate by choosing the value of Nfrom 1 to 8
where f
s
= MCLK/(128
Selects the PLL. If the PLL is selected, the sampling rate is set to MCLK/(128
the PLL is bypassed, the sampling rate can be set to MCLK/(512
N) or MCLK/(512
N)
N). If
N).
Register 5
Reserved for factory test. Do not write to this register.
Register 6
Reserved for factory test. Do not write to this register.
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相關代理商/技術參數
參數描述
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