參數(shù)資料
型號(hào): TLC320AD52C
廠商: Texas Instruments, Inc.
英文描述: Sigma-Delta Analog Interface Circuits With Master-Slave Function(帶主從功能的∑△模擬接口電路,高分辨率信號(hào)轉(zhuǎn)換)
中文描述: sigma - delta模擬接口電路的主從功能(帶主從功能的Σ△模擬接口電路,高分辨率信號(hào)轉(zhuǎn)換)
文件頁數(shù): 11/59頁
文件大小: 306K
代理商: TLC320AD52C
1–5
1.5
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
PT
28
DW
21
FSD
O
Frame sync delayed output. The FSD (active-low) output synchronizes a slave
device to the frame sync of the master device. FSD is applied to the slave FS
input and is the same duration as the master FS signal but is delayed in time by
the number of shift clocks programmed in the control 3 register.
INM
2
6
I
Inverting input to analog modulator. INM requires an external single-pole
antialias filter with a low output impedance.
INP
1
5
I
Noninverting input to analog modulator. INP requires an external single-pole
antialias filter with a low output impedance.
M/S
29
22
I
Master/slave select input. When M/S is high, the device is the master, and when
it is low, it is a slave.
MCLK
25
18
I
Master clock. MCLK derives the internal clocks of the sigma–delta analog
interface circuit.
MONOUT
40
27
O
Monitor output. MONOUT allows for monitoring of the analog input and is a
high-impedance output. The gain or mute is selected using control 1 register.
OUTM
36
24
O
Inverting output of the DAC. The OUTM output can be loaded with 600
.
OUTM
is functionally identical with and complementary to OUTP. OUTM can also be
used alone for single-ended operation.
OUTP
35
23
O
Noninverting output of the DAC. The OUTP output can be loaded with 600
.
OUTP can also be used alone for single-ended operation.
PWRDWN
22
16
I
Power down. When PWRDWN is pulled low, the device goes into a power-down
mode, the serial interface is disabled, and most of the high-speed clocks are
disabled. However, all the register values are sustained and the device resumes
full power operation without reinitialization when PWRDWN is pulled high again.
PWRDWN resets the counters only and preserves the programmed register
contents (see paragraph 2.2.2 for more information).
REFM
46
2
O
Voltage reference filter input. REFM is provided for low-pass filtering of the
internal bandgap reference. The optimal ceramic capacitor value is 0.1
μ
F and
should be connected between REFM and REFP. DC voltage at REFM is 0 V.
Voltage reference filter positive input. REFP is provided for low-pass filtering of
the internal bandgap reference. The optimal ceramic capacitor value is 0.1
μ
F
and should be connected between REFP and REFM. DC voltage at REFP is
3.2 V.
REFP
45
1
O
RESET
21
15
I
Reset. RESET initializes all of the internal registers to their default values. The
serial port can be configured to the default state accordingly. See section 6 and
paragraph 2.2.1 for more information.
Shift clock. The SCLK signal clocks serial data in through DIN and out through
DOUT during the frame-sync interval. When configured as an output (M/S high),
SCLK is generated internally by multiplying the frame-sync signal frequency by
256. When configured as an input (M/S low), SCLK is generated externally and
must be synchronous with the master clock and frame sync.
NOTE: All digital inputs and outputs are TTL compatible, unless otherwise noted (for DVDD = 5 V).
SCLK
26
19
I/O
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