參數(shù)資料
型號： TLC320AD52C
廠商： Texas Instruments, Inc.
英文描述： Sigma-Delta Analog Interface Circuits With Master-Slave Function(帶主從功能的∑△模擬接口電路,高分辨率信號轉(zhuǎn)換)
中文描述： sigma - delta模擬接口電路的主從功能（帶主從功能的Σ△模擬接口電路，高分辨率信號轉(zhuǎn)換）
文件頁數(shù)： 15/59頁
文件大?。?/td> 306K
代理商： TLC320AD52C
2–1
2 Detailed Description
2.1
Device Functions
2.1.1
Operating Frequencies
If the sampling frequency is higher than 7 kHz, the sampling frequency is derived from the master clock
(MCLK) input by either equation 1 or 2.
MCLK
128
MCLK
512
fs
Sampling (conversion) frequency
N
(when bit D7 of register 4 is set to 0) (1)
fs
Sampling (conversion) frequency
N
(when bit D7 of register 4 is set to 1) (2)
If the sampling frequency is lower than 7 kHz, the sampling frequency is derived from the master clock
(MCLK) using equation 2 only, which bypasses the PLL. Equation 2 mustbe used in this case because the
PLL input clock for sampling frequencies lower than 7 kHz is outside of the working range for the PLL input
clock.
The inverse of the sampling frequency is the time between the falling edges of two successive primary
frame-sync signals. This time is the conversion period.
For example, to set the conversion rate to 8 kHz:
When bit D7 of register 4 is set to 0, use equation 1 to determine MCLK (MCLK = 128
×
N
×
8000)
When bit D7 of register 4 is set to 1, use equation 2 to determine MCLK (MCLK = 512
×
N
×
8000)
To set the conversion rate to 4 kHz:
Bit D7 of register 4 mustbe set to 1 to bypass the PLL, then use equation 2 to determine MCLK
(MCLK = 512
×
N
×
4000)
2.1.2
The input signal is amplified and applied to the ADC input. The ADC converts the signal into discrete output
digital words in 2’s-complement data format, corresponding to the instantaneous analog-signal value at the
sampling time. These 16-bit (or 15-bit) digital words, representing sampled values of the analog input signal
after the PGA, are clocked out of the serial port (DOUT) at the positive edge of SCLK during the frame-sync
interval, one bit for each SCLK and one word for each primary communication interval (256 SCLKs).
ADC Signal Channel
During secondary communication, the data previously programmed into the registers can be read out. This
read operation is accomplished by sending the appropriate register address (DS12 – DS8) with the read
bit (DS13) set to 1 in through DIN during present secondary communication. If a register read is not
requested, all 16 bits are cleared to 0 in the secondary communication. The timing sequence is shown in
figure 2–1 and figure 2–2.
相關(guān)PDF資料
PDF描述
TLC320AD55C Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口)
TLC320AD56(中文) Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口)
TLC320AD56C Sigma-Delta Analog Interface Circuit
tlc320ad56c Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口電路)
TLC320AD57(中文) Sigma-Delta Analog Interface Circuit(Sigma-Delta立體聲音頻ADC)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLC320AD52CDW 制造商:TI 制造商全稱:Texas Instruments 功能描述:SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION
TLC320AD52CPT 功能描述:IC ANALOG INTERFACE W/MS 48-LQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:PCM 數(shù)據(jù)接口:PCM 音頻接口 分辨率（位）:15 b ADC / DAC 數(shù)量:1 / 1 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):- 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):- 電壓 - 電源，模擬:2.7 V ~ 3.3 V 電壓 - 電源，數(shù)字:2.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:80-VFBGA 供應(yīng)商設(shè)備封裝:80-BGA MICROSTAR JUNIOR（5x5） 包裝:帶卷 (TR) 其它名稱:296-21257-2
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TLC320AD535C 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC
TLC320AD535C-I 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC
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