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參數(shù)資料
| 型號： | TLC320AD52C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Sigma-Delta Analog Interface Circuits With Master-Slave Function(帶主從功能的∑△模擬接口電路,高分辨率信號轉(zhuǎn)換) |
| 中文描述： | sigma - delta模擬接口電路的主從功能（帶主從功能的Σ△模擬接口電路，高分辨率信號轉(zhuǎn)換） |
| 文件頁數(shù)： | 16/59頁 |
| 文件大?。?/td> | 306K |
| 代理商： | TLC320AD52C |
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2–2
SCLK
FS
DOUT
(16-Bit)
DOUT
(15+1-Bit)
16 SCLKs
MSB
MSB
LSB
LSB
D15
D15
D14
D14
D1
D1
D0
M/S
1
2
15
16
17
NOTES: A. M/S is used to indicate whether the 15-bit data comes from master device or slave device.
(Master: M/S = 1, Slave M/S = 0)
B. The MSB (D15) is stable (the host can latch the data in at this time) at the falling edging of SCLK #1, the
last bit (D0,M/S) is stable at the falling edging of SCLK #16.
Figure 2–1. Timing Sequence of ADC Channel (Primary Communication Only)
FS
DOUT
(16-Bit)
16 SCLKs
16-Bit ADC Data
M/S + Register Address +
Register Data/
M/S + Register Address +
All 0s (see Note)
16 SCLKs
Primary
Secondary
Primary
DOUT
(15 +1-Bit)
15-Bit ADC Data
+ M/S
M/S + Register Data/
M/S + All 0 (see Note)
128 SCLKs
256 SCLKs
NOTE: M/S bit (DS15) in the secondary communication is used to indicate whether the register data (address and
content) comes from the master device or the slave device if the read bit is set. During register read operations,
bits DS7 – DS0 are the contents of the specified register. In register write operations, bits DS7 – DS0 are all 0s.
Figure 2–2. Timing Sequence of ADC Channel (Primary and Secondary Communication)
2.1.3
DIN receives the 16-bit serial data word (2’s complement) from the host during the primary communications
interval. These 16-bit digital words, representing the analog output signal before PGA, are clocked into the
serial port (DIN) at the falling edge of SCLK during the frame-sync interval, one bit for each SCLK and one
word for each primary communication interval (256 SCLKs). The data are converted to a pulse train by the
sigma–delta DAC, which consists of a digital interpolation filter and a digital modulator. The output of the
modulator is then passed to an internal low-pass filter to complete the analog signal reconstruction. Finally,
the resulting analog signal is applied to the input of a programmable-gain amplifier, which is capable of
driving a 600-
load differentially at OUTP and OUTM. The timing sequence is shown in figure 2–3.
DAC Signal Channel
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| TLC320AD55C | Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口) |
| TLC320AD56(中文) | Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口) |
| TLC320AD56C | Sigma-Delta Analog Interface Circuit |
| tlc320ad56c | Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口電路) |
| TLC320AD57(中文) | Sigma-Delta Analog Interface Circuit(Sigma-Delta立體聲音頻ADC) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC320AD52CDW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION |
| TLC320AD52CPT | 功能描述:IC ANALOG INTERFACE W/MS 48-LQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:PCM 數(shù)據(jù)接口:PCM 音頻接口 分辨率（位）:15 b ADC / DAC 數(shù)量:1 / 1 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):- 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):- 電壓 - 電源，模擬:2.7 V ~ 3.3 V 電壓 - 電源，數(shù)字:2.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:80-VFBGA 供應(yīng)商設(shè)備封裝:80-BGA MICROSTAR JUNIOR（5x5） 包裝:帶卷 (TR) 其它名稱:296-21257-2 |
| TLC320AD535 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC |
| TLC320AD535C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC |
| TLC320AD535C-I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC |
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