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參數(shù)資料
| 型號(hào)： | TFRA08C13 |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 98/188頁 |
| 文件大?。?/td> | 3047K |
| 代理商： | TFRA08C13 |
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Preliminary Data Sheet
October 2000
TFRA08C13 OCTAL T1/E1 Framer
98
L Lucent Technologies Inc.
Framer-System Interface
DS1 Modes
The DS1 framing formats require rate adaptation from
the 1.544 Mbits/s line interface bit stream to the system
interface which functions at multiples of a 2.048 Mbits/s
bit stream. The rate adaptation results in the need for
eight stuffed time slots on the system interface since
there are only 24 DS1 (1.544 Mbits/s) payload time
slots while there are 32 system (2.048 Mbits/s) time
slots. Placement of the stuffed time slots is defined by
register FRM_PR43 bit 0—bit 2.
CEPT Modes
The framer maps the line time slots into the corre-
sponding system time slot one-to-one. Framing time
slot 0, the FAS and NFAS bytes, are placed in system
time slot 0.
Receive Elastic Store
The receive interface between the framer and the sys-
tem CHI includes a 2-frame elastic store buffer to
enable rate adaptation. The receive line elastic store
buffer contains circuitry that monitors the read and
write pointers for potential data overrun and underrun
(slips) conditions. Whenever this slip circuitry deter-
mines that a slip may occur in the receive elastic store
buffer, it will adjust the read pointer such that a con-
trolled slip is performed. The controlled slip is imple-
mented by dropping or repeating a complete frame at
the frame boundaries. The occurrence of controlled
slips in the receive elastic store are indicated in the sta-
tus register FRM_SR3 bit 6 and bit 7.
Transmit Elastic Store
The transmit interface between the framer and the sys-
tem CHI includes a 2-frame elastic store buffer to
enable rate adaptation. The line transmit clock applied
to PLLCK[1—8] must be phase-locked to CHICK. No
indication of a slip in the transmit elastic store is given.
Concentration Highway Interface
Each framer has a dual, high-speed, serial interface to
the system known as the CHI. This flexible bus archi-
tecture allows the user to directly interface to other
Lucent components which use this interface, as well as
to Mitel* and AMD
TDM highway interfaces, with no
glue logic. Configured via the highway control registers
FRM_PR45 through FRM_PR66, this interface can be
set up in a number of different configurations.
The following is a list of the CHI features:
I
Lucent Technologies standard interface for communi-
cation devices.
I
Two pairs of transmit and receive paths to carry data
in 8-bit time slots.
I
Programmable definition of highways through offset
and clock-edge options which are independent for
transmit and receive directions.
I
Programmable idle code substitution of received time
slots.
I
Programmable 3-state control of each transmit time
slot.
I
Independent transmit and receive framing signals to
synchronize each direction of data flow.
I
An 8 kHz frame synchronization signal internally
generated from the received line clock.
I
Compatible with Miteland AMDPCM highways.
Supported is the optional configuration of the CHI
which presents the signaling information along with the
data in any framing modes when the device is pro-
grammed for the associated signaling mode (ASM).
This mode is discussed in the signaling section.
Data can be transmitted or received on either one of
two interface ports, called CHIDATA and CHIDATAB.
The user-supplied clock (CHICLK) controls the timing
on the transmit or receive paths. Individual time slots
are referenced to the frame synchronization (CHIFS)
pulse. Each frame consists of 32 time slots at a pro-
grammable data rate of 2.048 Mbits/s, 4.096 Mbits/s, or
8.192 Mbits/s requiring a clock (CHICK) of the same
rate. The clock and data rates of the transmit and
receive highways are programmed independently.
* Mitel s a registered trademark of Mitel Corporation.
AMD is a registered trademark of Advanced Micro Devices, Inc.
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相關(guān)代理商/技術(shù)參數(shù) |
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| TFRA08C13-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:TFRA08C13 OCTAL T1/E1 Framer |
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| TFRA84J131BL-3-DB | 制造商:LSI Corporation 功能描述:Framer DS0/DS1/DS2/DS3/E1/E2/E3 1.5V/3.3V 909-Pin BGA |
| TFRA84J13DS0 | 制造商:AGERE 制造商全稱:AGERE 功能描述:Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
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