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Lucent Technologies Inc.
139
Preliminary Data Sheet
October 2000
TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture
(continued)
Table 98. NT1-RE Unavailable Seconds Counter (FRM_SR50—FRM_SR51) (Y32—Y33)
Received NOT-FAS TS0 RSa Register (FRM_SR52)
This register contains the last (since last read) valid received RSa8— RSa4 bits, A bit, and Si bit of NOT-FAS time
slot 0 and the Si bit of FAS time slot 0 while the receive framer was in basic frame alignment.
Table 99. Receive NOT-FAS TS0 Register (FRM_SR52) (Y34)
Received Sa Register (FRM_SR53)
This register contains the last (since last read) valid time slot 16 spare bits of the frame containing the time slot 16
signaling multiframe alignment. These bits are updated only when the receive framer is in signaling multiframe
alignment.
Table 100. Receive Sa Register (FRM_SR53) (Y35)
SLC-96 FDL/CEPT Sa Receive Stack (FRM_SR54—FRM_SR63)
In the SLC-96 frame format, FRM_SR54 through FRM_SR58 contain the received SLC-96 facility data link data
block. When the framer is in a loss of frame alignment or loss of signaling superframe alignment, these registers
are
not
updated.
Note:
The RSP[1:4] are the received spoiler bits.
Table 101.SLC-96 FDL Receive Stack (FRM_SR54—FRM_SR63) (Y36—Y3F)
Register
FRM_SR50
FRM_SR51
Byte
MSB
LSB
Bit
7—0
7—0
Symbol
Description
NTREUS15—NTREUS8
NTREUS7—NTREUS0
NT1-RE Unavailable Seconds Counter Bits.
NT1-RE Unavailable Seconds Counter Bits.
Bit 7
Bit 6
FAS bit 1
Bit 5
A bit
Bit 4
Sa4
Bit 3
Sa5
Bit 2
Sa6
Bit 1
Sa7
Bit 0
Sa8
NOT-FAS bit 1
(CEPT without CRC-4)
or
frame 15 E bit
(CEPT with CRC-4)
(CEPT without CRC-4)
or
frame 13 E bit
(CEPT with CRC-4)
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
X2
Bit 1
X1
Bit 0
X0
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FRM_SR54
FRM_SR55
FRM_SR56
FRM_SR57
FRM_SR58
FRM_SR59—
FRM_SR61
0
0
0
0
R-0
R-0
RC3
RC11
RA2
0
R-0
R-0
RC4
R-0
R-0
RC5
R-1
R-1
RC6
R-1
R-1
RC7
RM1
RS4
0
R-1
R-1
RC8
RM2
RC1
RC9
RM3
0
RC2
RC10
RA1
0
RSPB1 = 0 RSPB2 = 1 RSPB3 = 0
RS1
RS2
0
0
RS3
0
RSPB4 = 1
0