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參數(shù)資料
| 型號： | TFRA08C13 |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 70/188頁 |
| 文件大小： | 3047K |
| 代理商： | TFRA08C13 |
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Preliminary Data Sheet
October 2000
TFRA08C13 OCTAL T1/E1 Framer
70
L Lucent Technologies Inc.
Alarms and Performance Monitoring
(continued)
I
Received
bipolar violation errors
alarm, FRM_SR3
bit 0. This alarm indicates any bipolar decoding error
or detection of excessive zeros.
I
Received
excessive CRC errors
alarm, FRM_SR3
bit 3. In ESF, this alarm is asserted when 320 or
more CRC-6 checksum errors are detected within a
one second interval. In CEPT, this alarm is asserted
when 915 or more CRC-4 checksum errors are
detected within a one second interval.
I
The CEPT
continuous E-bit
alarm (CREBIT)
(FRM_SR2 bit 2). CREBIT is asserted when the
receive framer detects the following:
— Five consecutive seconds where each 1 s interval
contains
≥
991 received E bits = 0 events.
— Simultaneously no LFA occurred.
— Optionally, no remote frame alarm (A bit = 1) was
detected if register FRM_PR9 bit 0, bit 4, and bit 5
are set to 1.
— Optionally, neither Sa6-F
hex
nor Sa6-E
hex
codes
were detected if register FRM_PR9 bit 0, bit 4,
and bit 6 are set to 1.
The 5 s timer is started when the following occurs:
— CRC-4 multiframe alignment is achieved.
— And optionally, A = 0 is detected if register
FRM_PR9 bit 0, bit 4, and bit 5 are set to 1.
— And optionally, neither Sa6
_
F
hex*
nor Sa6
_
E
hex*
is
detected if register FRM_PR9 bit 0, bit 4, and bit 6
are set to 1.
The 5 s counter is restarted when the following
occurs:
— LFA occurs, or
—
≥
990 E bit = 0 events occur in 1 s, or
— Optionally, an A bit = 1 is detected if register
FRM_PR9 bit 0, bit 4, and bit 5 are set to 1.
— Optionally, a valid Sa6 pattern 1111 (binary) or
Sa6 pattern 1110 (binary) code was detected if
register FRM_PR9 bit 0, bit 4, and bit 6 are
set to 1.
This alarm is disabled during loss of frame alignment
(LFA) or loss of CRC-4 multiframe alignment
(LTS0MFA).
I
Failed state
alarm or the
unavailable state alarm
,
FRM_SR5 bit 3 and bit 7 and FRM_SR6 bit 3 and bit
7. This alarm is defined as the unavailable state at
the onset of ten consecutive severely errored sec-
onds. In this state, the receive framer inhibits incre-
menting of the severely errored and errored second
counters for the duration of the unavailable state. The
receive framer deasserts the unavailable state condi-
tion at the onset of ten consecutive errored seconds
which were not severely errored.
I
The
4-bit Sa6 codes
(FRM_SR2 bit 3—bit 7). Sa6
codes are asserted if three consecutive 4-bit pat-
terns have been detected. The alarms are disabled
when three consecutive 4-bit Sa6 codes have been
detected that are different from the pattern previously
detected. The receive framer monitors the Sa6 bits
for special codes described in ETSI ETS 300 233:
May 1994, Section 9.2. The Sa6 codes are defined in
Table 29 and Table 30. The Sa6 codes in Table 29
may be recognized as an asynchronous bit stream in
either non-CRC-4 or CRC-4 modes as long as the
receive framer is in the basic frame alignment state.
In the CRC-4 mode, the receive framer can optionally
recognize the received Sa6 codes in Table 29 syn-
chronously to the CRC-4 submultiframe structure as
long as the receive framer is in the CRC-4 multiframe
alignment state (synchronous Sa6 monitoring can be
enabled by setting register FRM_PR10 bit 1 to 1).
The Sa6 codes in Table 30 are only recognized syn-
chronously to the CRC-4 submultiframe and when
the receive framer is in CRC-4 multiframe alignment.
The detection of three (3) consecutive 4-bit patterns
are required to indicate a valid received Sa6 code.
The detection of Sa6 codes is indicated in status reg-
ister FRM_SR2 bit 3—bit 7. Once set, any three-nib-
ble (12-bit) interval that contains any other Sa6 code
will clear the current Sa6 status bit. Interrupts may be
generated by the Sa6 codes given in Table 29
* See Table 29, for the definition of this Sa6 pattern.
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