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參數(shù)資料
| 型號(hào)： | TFRA08C13 |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 62/188頁(yè) |
| 文件大小： | 3047K |
| 代理商： | TFRA08C13 |
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Preliminary Data Sheet
October 2000
TFRA08C13 OCTAL T1/E1 Framer
62
L Lucent Technologies Inc.
Signaling Access
(continued)
Table 23 illustrates the ASM time-slot format for valid channels.
Table 23. Associated Signaling Mode CHI 2-Byte Time-Slot Format for DS1 Frames
* X indicates bits that are undefined by the framer.
The identical sense of the received system P bit in the transmitted signaling data is echoed back to the system in the received
signaling information.
The DS1 framing formats require rate adaptation from the line-interface 1.544 Mbits/s bit stream to the system-
interface 4.096 Mbits/s bit stream. The rate adaptation results in the need for stuffed time slots on the system inter-
face. Table 24 illustrates the ASM format for T1 stuffed channels used by the TFRA08C13. The stuffed data byte
contains the programmable idle code in register FRM_PR23 (default = 7F (hex)), while the signaling byte is
ignored.
Table 24. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels
* X indicates bits which are undefined by the framer.
CEPT: Time Slot 16 Signaling
Microprocessor Control Registers
To enable signaling, register FRM_PR44 bit 0 must be set to 0 (default).
The information written into transmit signaling control registers FRM_TSR0—FRM_TSR31 define the state of the
ABCD bits of time slot 16 transmitted to the line.
The received signaling data from time slot 16 is stored in receive signaling registers FRM_RSR0—FRM_RSR31.
Associated Signaling Mode
Signaling information in the associated signaling mode (ASM), register FRM_PR44 bit 2 = 1, is allocated an 8-bit
system time slot in conjunction with the data information for a particular channel. The default system data rate in
the ASM mode is 4.096 Mbits/s. Each system channel consists of an 8-bit payload time slot followed by its associ-
ated 8-bit signaling time slot. The format of the signaling byte is identical to the signaling registers.
Table 25 illustrates the ASM time-slot format for valid CEPT E1 time slots
Table 25. Associated Signaling Mode CHI 2-Byte Time-Slot Format for CEPT
* In the CEPT formats, these bits are undefined.
The P bit is the parity-sense bit calculated over the 8 data bits, the ABCD (and E) bits, and the P bit. The identical sense of the received
system P bit in the transmitted signaling data is echoed back to the system in the received signaling information.
DS1: ASM CHI Time Slot
PAYLOAD DATA
4
SIGNALING INFORMATION*
C
D
1
2
3
5
6
7
8
A
B
X
F
G
P
ASM CHI Time Slot
PAYLOAD DATA
1
SIGNALING INFORMATION*
X
X
0
1
1
1
1
1
1
X
X
X
X
X
X
CEPT ASM CHI Time Slot
PAYLOAD DATA
4
SIGNALING INFORMATION
C
D
1
2
3
5
6
7
8
A
B
E
X
*
X
*
P
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TFRA08C13 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| TFS380C | VI TELEFILTER Filter specification |
| TFT0675F | Anti-Aliasing and Reconstruction TFT range |
| TFT0675S | Anti-Aliasing and Reconstruction TFT range |
| TFT1350F | Anti-Aliasing and Reconstruction TFT range |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TFRA08C13-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:TFRA08C13 OCTAL T1/E1 Framer |
| TFRA28J133BAL-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| TFRA84J13 | 制造商:AGERE 制造商全稱:AGERE 功能描述:Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| TFRA84J131BL-3-DB | 制造商:LSI Corporation 功能描述:Framer DS0/DS1/DS2/DS3/E1/E2/E3 1.5V/3.3V 909-Pin BGA |
| TFRA84J13DS0 | 制造商:AGERE 制造商全稱:AGERE 功能描述:Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
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