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參數(shù)資料
| 型號(hào)： | TDA8757CHV/21 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-612-1, HLQFP-144 |
| 文件頁(yè)數(shù)： | 9/38頁(yè) |
| 文件大?。?/td> | 894K |
| 代理商： | TDA8757CHV/21 |
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Philips Semiconductors
TDA8757C
Triple 8-bit ADC 205 Msps
Preliminary data
Rev. 01 — 14 August 2002
17 of 38
9397 750 10111
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
If an external clock is used, it has to be connected to pin CKEXT. Bit ‘Ckext’ and
bit ‘Ckrs’ in the phase register have to be set at logic 1. It is also important to
disconnect the internal PLL by using the following settings:
Set bit ‘Do’ in the control register to logic 1.
Set bits ‘Vco1’ and ‘Vco0’ in register VCO to logic 0.
There is a delay (tCKREFO) between the input signal on pin CKREF and the
corresponding output on pin CKREFO; see Figure 8.
tCKREFO = either tCKAO (if clock phase >01000) or tCKAO +TCLK(pixel) (if phase <01000)
tCKAO =tCLK(buffer) +tphase selector
tCLK(buffer) = tbf and tphase selector =
9.
I2C-bus and 3W-bus interfaces
9.1 Register denitions
The conguration of the registers is given in Table 4.
Fig 8.
Timing diagram; CKREFO; Dmx = 0.
CKREF
CKADC
CKREFO
Ckrp = 0
CKREFO
Ckrp = 1
8 clock periods
FCE699
tCKAO
tCKREFO
phase
2
π
---------------
T
CLK pixel
()
Table 4:
I2C-bus and 3W-bus registers
Function
name
Subaddress
Bit denition
Default
value
A7 A6 A5 A4 A3 A2 A1 A0 MSB
LSB
SUBADDR
X
Mode Sa3
Sa2
Sa1
Sa0
XXX1 0000
OFFSETR
XXXX
0000Or7
Or6
Or5
Or4
Or3
Or2
Or1
Or0
0111 1111
COARSER XXXX
0001Or8
Cr6
Cr5
Cr4
Cr3
Cr2
Cr1
Cr0
0010 0000
FINER
XXXX
0010PWD
Testvol Testvoh Fr4
Fr3
Fr2
Fr1
Fr0
0000 0000
OFFSETG
XXXX
0011Og7
Og6
Og5
Og4
Og3
Og2
Og1
Og0
0111 1111
COARSEG XXXX
0100Og8
Cg6
Cg5
Cg4
Cg3
Cg2
Cg1
Cg0
0010 0000
FINEG
XXXX
0101SW2
SW1
SlevelFg4
Fg3
Fg2
Fg1
Fg0
0000 0000
OFFSETB
XXXX
0110Ob7
Ob6
Ob5
Ob4
Ob3
Ob2
Ob1
Ob0
0111 1111
COARSEB XXXX
0111Ob8
Cb6
Cb5
Cb4
Cb3
Cb2
Cb1
Cb0
0010 0000
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