參數(shù)資料
型號: TDA8757CHV/21
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-612-1, HLQFP-144
文件頁數(shù): 10/38頁
文件大?。?/td> 894K
代理商: TDA8757CHV/21
Philips Semiconductors
TDA8757C
Triple 8-bit ADC 205 Msps
Preliminary data
Rev. 01 — 14 August 2002
18 of 38
9397 750 10111
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
9.1.1
Subaddress
All the registers are dened by a subaddress of 7 bits: bit Mode refers to the mode
which is used with the I2C-bus interface, bits ‘Sa3’ to ‘Sa0’ give the subaddress of
each register.
Bit Mode, used only with the I2C-bus, allows two modes for the programming:
Mode 0
Each register is programmed independently, by giving its subaddress
and its content.
Mode 1
All the registers are programmed one after the other, by giving this initial
condition (XXX1 1111) as the subaddress state; thus, the registers are
changed following the predened sequence of 16 bytes (from
subaddress 0000 to 1101).
The default values correspond to a VESA 1280
× 1024 at 75 Hz graphic mode.
9.1.2
Offset register
This register controls the clamp level for the RGB channels. The relationship between
the programming code and the level of the clamp code is given in Table 5.
FINEB
XXXX
1000X
X
Cken
Fb4
Fb3
Fb2
Fb1
Fb0
XX00 0000
CONTROL XXXX
1001Vlevel Hlevel
Edge
Up
Do
Ip2
Ip1
Ip0
0000 0111
VCO
XXXX
1010Z2
Z1
Z0
Vco1
Vco0
Di11
Di10
Di9
1011 1011
DIVIDER
(LSB)
XXXX
1011Di8
Di7
Di6
Di5
Di4
Di3
Di2
Di1
0100 1100
PHASE
XXXX
1100Di0
Ckrs
Ckext
P4
P3
P2
P1
P0
0000 0000
DEMUX
XXXX
1101Blk
Shpixel Ckrp
Ckdp Ckdd Shift
Odda Dmx
1000 0111
Table 4:
I2C-bus and 3W-bus registers…continued
Function
name
Subaddress
Bit denition
Default
value
A7 A6 A5 A4 A3 A2 A1 A0 MSB
LSB
Table 5:
Coding
Programmed code
Clamp code
ADC output
0
63.5
underow
1
63
2
62.5
...
127
0
...
254
63.5
63 or 64
255
64
256
120
...
287
136
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