參數(shù)資料
型號: TDA8757CHV/21
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-612-1, HLQFP-144
文件頁數(shù): 4/38頁
文件大?。?/td> 894K
代理商: TDA8757CHV/21
Philips Semiconductors
TDA8757C
Triple 8-bit ADC 205 Msps
Preliminary data
Rev. 01 — 14 August 2002
12 of 38
9397 750 10111
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
8.
Functional description
This triple high-speed 8-bit ADC is designed to convert RGB/YUV signals, coming
from an analog source, into digital data used by a LCD driver (pixel clock up to
205 MHz).
8.1 Analog video inputs
The RGB/YUV video inputs are externally AC-coupled and are internally
DC polarized.
The synchronization signals are also used by the device for the internal PLL and the
gain calibration.
If the green video signal has composite sync (sync on green) it is possible to extract
this composite sync by connecting the green signal to pin INSOG (AC-coupled). When
the sync pulse amplitude is below 300 mV, the I2C-bus bit ‘Slevel’ has to be set to
logic 1 (see Figure 5). The maximum amplitude for the sync pulse is 600 mV typical.
The composite sync is available at pin SOGO (TTL level compatible signal).
If this function is not used, pin INSOG should be connected to the analog power
supply. In this event pin SOGO is at LOW-level TTL.
8.2 Clamps
Three independent parallel clamping circuits are used to clamp the video input
signals on several black levels. The clamping levels may be set from
63.5 to +64 LSBs (RGB) and from +120 to +136 LSBs in steps of 1
2 LSB (YUV).
They are controlled by changing the values in three 9-bit registers: OFFSETR,
OFFSETG and OFFSETB (see Table 5). Each clamp must be able to correct an
offset from
±100 mV to ±10 mV within 300 ns, and correct the total offset in 10 lines.
The clamping is done using the following principle: When a TTL positive going input
pulse is applied to pin CLP, three external capacitors are loaded independently by the
device in order to change the voltage level of each analog RGB input. The capacitors
are connected to pins CLPR, CLPG and CLPB.
Fig 5.
Sync level diagram.
blank level
150 mV comparison level
set by I2C-bus bit Slevel = 0
blank level
80 mV comparison level
set by I2C-bus bit Slevel = 1
150 mV
to
300 mV
to
600 mV
005aaa009
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