參數(shù)資料
型號(hào): TDA8295HN/C2
廠商: NXP SEMICONDUCTORS
元件分類: 接收器
英文描述: AM/FM, AUDIO/VIDEO DEMODULATOR, PQCC40
封裝: 6 X 6 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT618-1, HVQFN-40
文件頁數(shù): 41/83頁
文件大?。?/td> 3440K
代理商: TDA8295HN/C2
TDA8295_C2_2
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
46 of 83
NXP Semiconductors
TDA8295
Digital global standard low IF demodulator for analog TV and FM radio
9.3.18 Video and sound DAC control
The TDA8295 implements two 10-bit DAC modules (CVBS and sound outputs) which are
sampled by a 108 MHz clock. A reference module derives biasing currents for the two
DACs.
Table 52.
ADC_CTL_2 register (address 34h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7 to 2 -
R/W
-
not used
1
AD_PLL_BYP R/W
The clock PLL can be bypassed for the ADC sampling
clock. Then the crystal output is directly taken for ADC
sampling.
0*
Normal mode
1
Bypass mode
0
AD_SR54M
R/W
AD_SR54M sets the ADC sampling rate
0
ADC sampling rate 27 MHz; first decimation filter is
bypassed
1*
ADC sampling rate 54 MHz
Table 53.
VIDEODAC_CTL register (address 35h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7
-
R/W
0
reserved, must be set to logic 0
6 to 1 B_DA_V[5:0] R/W
B_DA_V is the coarse output level adjustment
parameters of the video DAC. See Section 13.3.
00 0000
minimum current setting
11 1111*
maximum current setting
0
PD_DA_V
R/W
When HIGH, PD_DA_V sets the video DAC into its
Power-down mode.
0*
Normal mode
1
video DAC Power-down mode
Table 54.
AUDIODAC_CTL register (address 36h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7
-
R/W
0
reserved, must be set to logic 0
6 to 1 B_DA_S[5:0] R/W
B_DA_S is the coarse output level adjustment
parameters of the sound DAC. See Section 13.3.
00 0000*
minimum current setting
11 1111
maximum current setting
0
PD_DA_S
R/W
When HIGH, PD_DA_S sets the sound DAC into its
Power-down mode.
0*
Normal mode
1
sound DAC Power-down mode
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