參數(shù)資料
型號(hào)： TDA8031HL
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： USB smart card reader (OTP or ROM)
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, MS-026, SOT-314-2, LQFP-64
文件頁數(shù)： 19/57頁
文件大?。?/td> 228K
代理商： TDA8031HL
2003 Jul 04
19
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
8.1.4.3
Mixed status register
The Mixed Status Register (MSR) relates the status of the cards presence contact PRES, the BGT counter, the FIFO
empty indication, the transmit/receive ready indicator TBE/RBF and the completion of clock switching to or from
1
2
f
int
.
Table 11
Mixed status register (address 0CH; read only); note 1
Note
1.
Bits TBE/RBF are cleared after reset; bit FE is set after reset.
Table 12
Description of the MSR bits; note 1
Note
1.
No bits within the MSR have an effect on INT0.
7
6
5
4
3
2
1
0
CLKSW
FE
BGT
PR
TBE/RBF
BIT
SYMBOL
DESCRIPTION
7
CLKSW
Clock switch: Bit CLKSW = 1 when the TDA8030; TDA8031 has performed a required
clock switch from
1
n
f
xtal
to
1
2
f
int
and is reset when the TDA8030; TDA8031 has
performed a required clock switch from
1
2
f
int
to
1
n
f
xtal
; the application will wait until this
bit has been set or reset before setting the microcontroller in power-down mode or
restarting sending commands after leaving power-down mode (only needed when the
clock is not stopped). This bit is also reset by RIU and at power-on.
FIFO Empty: Bit FE = 1 when the reception FIFO is empty; it is reset when at least one
character has been loaded in the FIFO.
Block Guard Time: In T = 1 protocol, the bit BGT is linked with a 22 ETU counter, which
is started at every start bit on the I/O. If the count is finished before the next start bit,
then bit BGT is set. This helps to ensure that the card has not answered before 22 ETU
after the last transmitted character, or that the reader is not transmitting a character
before 22 ETU after the last received character.
In T = 0 protocol, the bit BGT is linked to a 16 ETU counter, which is started at every
start bit on the I/O. If the count is finished before the next start bit, then the bit BGT is
set. This helps to ensure that the reader is not transmitting too early after the last
received character.
not used
Presence: Bit PR = 1 when the card is present.
not used
Transmit Buffer Empty/Receive Buffer Full: Bit TBE/RBF = 1 when:
Changing from reception mode to transmission mode
A character has been transmitted by the UART (except when a character has been
transmitted free of parity error while LCT = 1)
The reception buffer is full.
Bit TBE/RBF = 0 after power-on, or after one of the following:
When the bit RIU is reset
When a character has been written into register UTR
When the character has been read in register URR
When changing from transmission mode to reception mode.
6
FE
5
BGT
4 and 3
2
1
0
PR
TBE/RBF
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