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參數(shù)資料
| 型號： | TAS5711PHPR |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 64/66頁 |
| 文件大小： | 0K |
| 描述： | IC AMP AUD DGTL 20W 2CH 48HTQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | D 類 |
| 輸出類型： | 2 通道（立體聲，2.1）或 4 通道（四路） |
| 在某負(fù)載時最大輸出功率 x 通道數(shù)量： | 21W x 2 @ 8 歐姆 |
| 電源電壓： | 8 V ~ 26 V |
| 特點(diǎn)： | 消除爆音，數(shù)字輸入，I²C，I²S，靜音，短路和熱保護(hù)，關(guān)機(jī)，音量控制 |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 48-HTQFP（7x7） |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 860 (CN2011-ZH PDF) |
| 其它名稱： | 296-25564-6 |
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www.ti.com
SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010
PIN FUNCTIONS (continued)
PIN
5-V
TYPE(1)
TERMINATION(2)
DESCRIPTION
TOLERANT
NAME
NO.
DVSS
28
P
Digital ground
GND
29
P
Analog ground for power stage
GVDD_OUT
5, 32
P
Gate drive internal regulator output. This pin must not be used to
drive external devices.
LRCLK
20
DI
5-V
Pulldown
Input serial audio data left/right clock (sample rate clock)
MCLK
15
DI
5-V
Pulldown
Master clock input
OC_ADJ
7
AO
Analog overcurrent programming. Requires resistor to ground.
OSC_RES
16
AO
Oscillator trim resistor. Connect an 18.2-k
1% resistor to DVSSO.
OUT_A
1
O
Output, half-bridge A
OUT_B
46
O
Output, half-bridge B
OUT_C
39
O
Output, half-bridge C
OUT_D
36
O
Output, half-bridge D
PBTL
8
DI
Low means BTL or SE mode; high means PBTL mode. Information
goes directly to power stage.
PDN
19
DI
5-V
Pullup
Power down, active-low. PDN prepares the device for loss of power
supplies by shutting down the Noise Shaper and initiating PWM stop
sequence.
PGND_AB
47, 48
P
Power ground for half-bridges A and B
PGND_CD
37, 38
P
Power ground for half-bridges C and D
PLL_FLTM
10
AO
PLL negative loop filter terminal
PLL_FLTP
11
AO
PLL positive loop filter terminal
PVDD_A
2, 3
P
Power supply input for half-bridge output A
PVDD_B
44, 45
P
Power supply input for half-bridge output B
PVDD_C
40, 41
P
Power supply input for half-bridge output C
PVDD_D
34, 35
P
Power supply input for half-bridge output D
RESET
25
DI
5-V
Pullup
Reset, active-low. A system reset is generated by applying a logic
low to this pin. RESET is an asynchronous control signal that
restores the DAP to its default conditions, and places the PWM in
the hard mute state (tristated).
SCL
24
DI
5-V
I2C serial control clock input
SCLK
21
DI
5-V
Pulldown
Serial audio data clock (shift clock). SCLK is the serial audio port
input data bit clock.
SDA
23
DIO
5-V
I2C serial control data interface input/output
SDIN
22
DI
5-V
Pulldown
Serial audio data input. SDIN supports three discrete (stereo) data
formats.
SSTIMER
6
AI
Controls ramp time of OUT_x to minimize pop. Leave this pin
floating for BD mode. Requires capacitor of 2.2 nF to GND in AD
mode. The capacitor determines the ramp time.
STEST
26
DI
Factory test pin. Connect directly to DVSS.
VR_ANA
12
P
Internally regulated 1.8-V analog supply voltage. This pin must not
be used to power external devices.
VR_DIG
18
P
Internally regulated 1.8-V digital supply voltage. This pin must not be
used to power external devices.
VREG
31
P
Digital regulator output. Not to be used for powering external
circuitry.
Copyright 2009–2010, Texas Instruments Incorporated
7
Product Folder Link(s): TAS5711
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