參數(shù)資料
型號: TAS5711PHPR
廠商: Texas Instruments
文件頁數(shù): 20/66頁
文件大小: 0K
描述: IC AMP AUD DGTL 20W 2CH 48HTQFP
標(biāo)準(zhǔn)包裝: 1
類型: D 類
輸出類型: 2 通道(立體聲,2.1)或 4 通道(四路)
在某負(fù)載時最大輸出功率 x 通道數(shù)量: 21W x 2 @ 8 歐姆
電源電壓: 8 V ~ 26 V
特點: 消除爆音,數(shù)字輸入,I²C,I²S,靜音,短路和熱保護,關(guān)機,音量控制
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 48-HTQFP(7x7)
封裝/外殼: 48-TQFP 裸露焊盤
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 860 (CN2011-ZH PDF)
其它名稱: 296-25564-6
SCLK
16Clks
LRCLK
LeftChannel
16-BitMode
1
15
14
MSB
LSB
16Clks
RightChannel
2-ChannelI S(PhilipsFormat)StereoInput
2
T0266-01
3
2
5
4
9
8
0
13
10
11
12
SCLK
MSB
LSB
23
22
SCLK
32Clks
LRCLK
LeftChannel
24-BitMode
1
19
18
20-BitMode
16-BitMode
15
14
MSB
LSB
32Clks
RightChannel
2-ChannelLeft-JustifiedStereoInput
T0034-02
4
5
9
8
1
4
5
1
0
23
22
1
19
18
15
14
MSB
LSB
4
5
9
8
1
4
5
1
0
SCLK
www.ti.com
SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010
NOTE: All data presented in 2s-complement form with MSB first.
Figure 39. I2S 32-fS Format
Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK
toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused
trailing data bit positions.
NOTE: All data presented in 2s-complement form with MSB first.
Figure 40. Left-Justified 64-fS Format
Copyright 2009–2010, Texas Instruments Incorporated
27
Product Folder Link(s): TAS5711
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