參數(shù)資料
型號: TAS5711PHPR
廠商: Texas Instruments
文件頁數(shù): 25/66頁
文件大小: 0K
描述: IC AMP AUD DGTL 20W 2CH 48HTQFP
標準包裝: 1
類型: D 類
輸出類型: 2 通道(立體聲,2.1)或 4 通道(四路)
在某負載時最大輸出功率 x 通道數(shù)量: 21W x 2 @ 8 歐姆
電源電壓: 8 V ~ 26 V
特點: 消除爆音,數(shù)字輸入,I²C,I²S,靜音,短路和熱保護,關機,音量控制
安裝類型: 表面貼裝
供應商設備封裝: 48-HTQFP(7x7)
封裝/外殼: 48-TQFP 裸露焊盤
包裝: 標準包裝
產(chǎn)品目錄頁面: 860 (CN2011-ZH PDF)
其它名稱: 296-25564-6
7-BitSlave Address
R/
W
8-BitRegister Address(N)
A
8-BitRegisterDataFor
Address(N)
Start
Stop
SDA
SCL
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
A
8-BitRegisterDataFor
Address(N)
A
T0035-01
www.ti.com
SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010
I
2C SERIAL CONTROL INTERFACE
The TAS5711 DAP has a bidirectional I2C interface that compatible with the I2C (Inter IC) bus protocol and
supports both 100-kHz and 400-kHz data transfer rates for single and multiple byte write and read operations.
This is a slave only device that does not support a multimaster bus environment or wait state insertion. The
control interface is used to program the registers of the device and to read device status.
The DAP supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation
(400 kHz maximum). The DAP performs all I2C operations without I2C wait cycles.
General I2C Operation
The I2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially one bit at a time. The address and data can be transferred in byte
(8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data pin (SDA) while the clock is high to indicate a start and stop conditions. A
high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data bit
transitions must occur within the low time of the clock period. These conditions are shown in Figure 46. The
master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The TAS5711 holds SDA low during the acknowledge clock
period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence.
Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the
same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for
the SDA and SCL signals to set the high level for the bus.
Figure 46. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 46.
Pin A_SEL defines the I2C device address. An external 15-k
Ω pulldown on this pin gives a device address of
0x34 and a 15-k
Ω pullup gives a device address of 0x36. The 7-bit address is 0011011 (0x36) or 0011010
(0x34).
I2C Device Address Change Procedure
Write to device address change enable register, 0xF8 with a value of 0xF9 A5 A5 A5.
Write to device register 0xF9 with a value of 0x0000 00XX, where XX is the new address.
Any writes after that should use the new device address XX.
Single- and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses
0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only
multiple-byte read/write operations (in multiples of 4 bytes).
Copyright 2009–2010, Texas Instruments Incorporated
31
Product Folder Link(s): TAS5711
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