參數(shù)資料
型號(hào): TAS5711PHPR
廠商: Texas Instruments
文件頁數(shù): 50/66頁
文件大?。?/td> 0K
描述: IC AMP AUD DGTL 20W 2CH 48HTQFP
標(biāo)準(zhǔn)包裝: 1
類型: D 類
輸出類型: 2 通道(立體聲,2.1)或 4 通道(四路)
在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量: 21W x 2 @ 8 歐姆
電源電壓: 8 V ~ 26 V
特點(diǎn): 消除爆音,數(shù)字輸入,I²C,I²S,靜音,短路和熱保護(hù),關(guān)機(jī),音量控制
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 48-HTQFP(7x7)
封裝/外殼: 48-TQFP 裸露焊盤
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 860 (CN2011-ZH PDF)
其它名稱: 296-25564-6
SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010
www.ti.com
OSCILLATOR TRIM REGISTER (0x1B)
The TAS5711 PWM processor contains an internal oscillator to support autodetect of I2S clock rates. This
reduces system cost because an external reference is not required. Currently, TI recommends a reference
resistor value of 18.2 k
(1%). This should be connected between OSC_RES and DVSSO.
Writing 0x00 to register 0x1B enables the trim that was programmed at the factory.
Note that trim must always be run following reset of the device.
Table 18. Oscillator Trim Register (0x1B)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
1
Reserved (1)
0
Oscillator trim not done (read-only) (1)
1
Oscillator trim done (read only)
0
Reserved (1)
0
Select factory trim (Write a 0 to select factory trim; default is 1.)
1
Factory trim disabled (1)
0
Reserved (1)
(1)
Default values are in bold.
BKND_ERR REGISTER (0x1C)
When a back-end error signal is received from the internal power stage, the power stage is reset stopping all
PWM activity. Subsequently, the modulator waits approximately for the time listed in Table 19 before attempting
to re-start the power stage.
Table 19. BKND_ERR Register (0x1C)(1)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
X
Reserved
0
1
0
Set back-end reset period to 299 ms (2)
0
1
Set back-end reset period to 449 ms
0
1
0
Set back-end reset period to 598 ms
0
1
0
1
Set back-end reset period to 748 ms
0
1
0
Set back-end reset period to 898 ms
0
1
Set back-end reset period to 1047 ms
1
0
Set back-end reset period to 1197 ms
1
0
1
Set back-end reset period to 1346 ms
1
0
1
X
Set back-end reset period to 1496 ms
1
X
Set back-end reset period to 1496 ms
(1)
This register can be written only with a "non-Reserved" value. Also this register can be written once after the reset.
(2)
Default values are in bold.
54
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5711
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