參數(shù)資料
型號(hào)： TAS5711PHPR
廠商： Texas Instruments
文件頁(yè)數(shù)： 27/66頁(yè)
文件大小： 0K
描述： IC AMP AUD DGTL 20W 2CH 48HTQFP
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： D 類(lèi)
輸出類(lèi)型： 2 通道（立體聲，2.1）或 4 通道（四路）
在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量： 21W x 2 @ 8 歐姆
電源電壓： 8 V ~ 26 V
特點(diǎn)： 消除爆音，數(shù)字輸入，I²C，I²S，靜音，短路和熱保護(hù)，關(guān)機(jī)，音量控制
安裝類(lèi)型： 表面貼裝
供應(yīng)商設(shè)備封裝： 48-HTQFP（7x7）
封裝/外殼： 48-TQFP 裸露焊盤(pán)
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 860 (CN2011-ZH PDF)
其它名稱(chēng)： 296-25564-6
A6
A5
A0 R/W ACK A7
A6
A5
A4
A0 ACK
A6
A5
A0
ACK
Start
Condition
Stop
Condition
Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress
DataByte
D7
D6
D1
D0 ACK
I CDevice Addressand
Read/WriteBit
2
Not
Acknowledge
R/W
A1
RepeatStart
Condition
T0036-03
A6
A0
ACK
Acknowledge
I CDevice Addressand
Read/WriteBit
2
R/W
A6
A0
R/W ACK
A0 ACK
D7
D0
ACK
Start
Condition
Stop
Condition
Acknowledge
LastDataByte
ACK
FirstDataByte
RepeatStart
Condition
Not
Acknowledge
I CDevice Addressand
Read/WriteBit
2
Subaddress
OtherDataBytes
A7
A6
A5
D7
D0 ACK
Acknowledge
D7
D0
T0036-04
www.ti.com
SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010
Single-Byte Read
As shown in Figure 49, a single-byte data read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5711 address
and the read/write bit, TAS5711 responds with an acknowledge bit. In addition, after sending the internal memory
address byte or bytes, the master device transmits another start condition followed by the TAS5711 address and
the read/write bit again. This time the read/write bit becomes a 1, indicating a read transfer. After receiving the
address and the read/write bit, the TAS5711 again responds with an acknowledge bit. Next, the TAS5711
transmits the data byte from the memory address being read. After receiving the data byte, the master device
transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer.
Figure 49. Single-Byte Read Transfer
Multiple-Byte Read
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TAS5711 to the master device as shown in Figure 50. Except for the last data byte, the
master device responds with an acknowledge bit after receiving each data byte.
Figure 50. Multiple Byte Read Transfer
Copyright 2009–2010, Texas Instruments Incorporated
33
Product Folder Link(s): TAS5711
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