參數(shù)資料
型號： SX52BD
廠商： Electronic Theatre Controls, Inc.
英文描述： Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability, and On-Chip Debug
中文描述： 配置通信控制器與電子工程/閃存程序存儲器，在系統(tǒng)編程能力，以及片上調(diào)試
文件頁數(shù)： 40/58頁
文件大?。?/td> 873K
代理商： SX52BD
2002 Ubicom, Inc. All rights reserved.
- 40 -
www.ubicom.com
SX48BD/SX52BD
14.0
DIFFERENT RESET CONDITIONS
The effect of different reset operations on a register
depends on the register and the type of reset operation.
Some registers are initialized to specific values, some
are left unchanged, some are undefined, and some are
initialized to an unknown value.
REGISTER STATES UPON
A register that starts with an unknown value should be
initialized by the software to a known value; you cannot
simply test the initial state and rely on it starting in that
state consistently. Table 14-1 lists the SX registers and
shows the state of each register upon reset, with a differ-
ent column for each type of reset.
Table 14-1. Register States Upon Different Resets
Register
Power-On
Wakeup
Brown-out
Watchdog
Timeout
Unchanged
FFh
1Fh
Unchanged
FFh
Bits 0-2: Un-
changed
Bits 3-4: (Note 1)
Bits 5-7: 000
Bits 0-6: Un-
changed
Bit 7: 1
FFh
MCLR
W
OPTION
MODE (Note 3)
RTCC (01h)
PC (02h)
STATUS (03h)
(Note 3)
Undefined
FFh
1Fh
Undefined
FFh
Bits 0-2: Unde-
fined
Bits 3-4: 11
Bits 5-7: 000
Undefined
Unchanged
FFh
1Fh
Unchanged
FFh
Bits 0-2: Un-
changed
Bits 3-4: Unch.
Bits 5-7: 000
Bits 0-6: Un-
changed
Bit 7: 1
FFh
Undefined
FFh
1Fh
Undefined
FFh
Bits 0-4: Unde-
fined
Bits 5-7: 000
Unchanged
FFh
1Fh
Unchanged
FFh
Bits 0-2: Un-
changed
Bits 3-4: (Note 2)
Bits 5-7:000
Bits 0-6: Un-
changed
Bit 7: 1
FFh
FSR (04h)
Bits 0-6: Unde-
fined
Bit 7: 1
FFh
RA through RE
Direction
RA through RE Data
Other File Registers -
SRAM
CMP_B
FFh
Undefined
Undefined
Unchanged
Unchanged
Undefined
Undefined
Unchanged
Unchanged
Unchanged
Unchanged
Bits 0, 6-7: 1
Bits 1-5: Unde-
fined
Undefined
FFh
FFh
FFh
FFh
FFh
Undefined
0001
Bits 0, 6-7: 1
Bits 1-5: Undefined
Bits 0, 6-7: 1
Bits 1-5: Unde-
fined
Undefined
FFh
FFh
FFh
FFh
FFh
Undefined
0001
Bits 0, 6-7: 1
Bits 1-5: Undefined
Bits 0, 6-7: 1
Bits 1-5: Undefined
WKPND_B
WKED_B
WKEN_B
ST_B through ST_E
LVL_A through LVL_E
PLP_A through PLP_E
Watchdog Counter
Timers T1 and T2 Free-
Running Timer/Counter
Timers T1 and T2 Com-
pare/Capture Registers
Timers T1 and T2 Control
Registers (Note 3)
NOTE:
1. Watchdog reset during power down mode: 00 (bits TO, PD)
Watchdog reset during Active mode: 01 (bits TO, PD)
Unchanged
FFh
FFh
FFh
FFh
FFh
Unchanged
0001
Unchanged
FFh
FFh
FFh
FFh
FFh
Unchanged
0001
Unchanged
FFh
FFh
FFh
FFh
FFh
Unchanged
0001
0000
0000
0000
0000
0000
00
00
00
00
00
NOTE:
2. External reset during power down mode: 10 (bits TO, PD)
External reset during Active mode: Unchanged (bits TO, PD)
Note:. 3. MODE, STATUS, and Timer registers are not initialized properly by the development system in Debug mode.
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