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參數(shù)資料
| 型號： | SX52BD |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability, and On-Chip Debug |
| 中文描述： | 配置通信控制器與電子工程/閃存程序存儲器，在系統(tǒng)編程能力，以及片上調(diào)試 |
| 文件頁數(shù)： | 23/58頁 |
| 文件大?。?/td> | 873K |
| 代理商： | SX52BD |
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2002 Ubicom, Inc. All rights reserved.
- 23 -
www.ubicom.com
SX48BD/SX52BD
7.0
The device supports both internal and external maskable
interrupts. The internal interrupt is generated as a result
of the RTCC rolling over from FFh to 00h. This interrupt
source has an associated enable bit located in the
OPTION register and pending flag bit in the Timer T1
Control B register. In addition, timers T1 and T2 each
have three interrupt sources associated with counter
overflow, compare match, and input capture.
Port B provides the source for eight external software
selectable, edge sensitive interrupts, when the device is
not in the power down mode. These interrupt sources
share logic with the Multi-Input Wakeup circuitry. The
WKEN_B register allows interrupt from Port B to be indi-
vidually enabled or disabled. Clearing a bit in the
INTERRUPT SUPPORT
WKEN_B register enables the interrupt on the corre-
sponding Port B pin. The WKED_B selects the transition
edge to be either positive or negative. The WKEN_B and
WKED_B registers are set to FFh upon reset. Setting a
bit in the WKED_B register selects the falling edge while
clearing the bit selects the rising edge on the correspond-
ing Port B pin.
The WKPND_B register serves as the external interrupt
pending register.
The WKPND_B register comes up with a random value
upon reset. The user program must clear the WKPND_B
register prior to enabling the interrupt.
Figure 7-1. Interrupt Structure
RTCC
WKED_B
I
WKED_B
WKPND_B
WKPND_B
From MODE
(MODE = 09/19)
OPTION
RTE_IE
WKEN_B
1 = Ext. Interrupt through Port B
0 = Sleep Mode, no Ext. Interrupt
STATUS
Register
PD Flag
Port B PIN
Interrupt
PC
000
Overflow
Device-Specific
Interrupt Sources
(e.g. Timer T1)
From MODE
(MODE = 0A/1A)
PC, STATUS, FSR, W, MODE
Interrupt Stack
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SX52BD/PQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability, and On-Chip Debug |
| SX52F | 制造商:PANJIT 制造商全稱:Pan Jit International Inc. 功能描述:SCHOTTKY BARRIER RECTIFIER |
| SX52F_R1_00001 | 制造商:PANJIT 制造商全稱:Pan Jit International Inc. 功能描述:SCHOTTKY BARRIER RECTIFIER |
| SX52F_R2_00001 | 制造商:PANJIT 制造商全稱:Pan Jit International Inc. 功能描述:SCHOTTKY BARRIER RECTIFIER |
| SX53F | 制造商:PANJIT 制造商全稱:Pan Jit International Inc. 功能描述:SCHOTTKY BARRIER RECTIFIER |
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