參數(shù)資料
型號: SX52BD
廠商: Electronic Theatre Controls, Inc.
英文描述: Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability, and On-Chip Debug
中文描述: 配置通信控制器與電子工程/閃存程序存儲器,在系統(tǒng)編程能力,以及片上調(diào)試
文件頁數(shù): 15/58頁
文件大小: 873K
代理商: SX52BD
2002 Ubicom, Inc. All rights reserved.
- 15 -
www.ubicom.com
SX48BD/SX52BD
4.3
OPTION Register
.
Upon reset, all bits in the OPTION register are set to 1.
4.4
DEVICE CONFIGURATION AND ID
REGISTERS
The SX device has two registers (FUSE, FUSEX) that
control functions such as clock oscillator configuration.
These registers are not programmable
on the fly
during
normal device operation. Instead, the FUSE and FUSEX
registers can only be accessed when the SX device is
being programmed. The DEVICE ID register is a read-
only, hard-wired register, defined during the manufactur-
ing process. Locations 1000h to 100Fh are allocated for
user code ID.
RTW
RTE
_IE
RTS
RTE
_ES
PSA
PS2
PS1
PS0
Bit 7
Bit 0
Bit 7: RTW
RTCC/W register selection:
0 = Register 01h addresses W
1 = Register 01h addresses RTCC
RTCC interrupt enable:
0 = RTCC roll-over interrupt is en-
abled
1 = RTCC roll-over interrupt is dis-
abled
RTCC increment select:
0 = RTCC increments on internal in-
struction cycle
1 = RTCC increments upon transition
on RTCC pin
RTCC edge select:
0 = RTCC increments on low-to-high
transitions
1 = RTCC increments on high-to-low
transitions
Prescaler Assignment:
0 = Prescaler is assigned to RTCC,
with divide rate determined by PS0-
PS2 bits
1 = Prescaler is assigned to WDT,
and divide rate on RTCC is 1:1
Bit 6: RTE_IE
Bit 5: RTS
Bit 4: RTE_ES
Bit 3: PSA
Bits 2-0: PS2-PS0 Prescaler divider (see Table 4-2)
Table 4-2. Prescaler Divider Ratios
PS2, PS1, PS0
RTCC
Divide
Rate
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Watchdog
Timer
Divide Rate
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
Approx.
Watchdog
Timeout (sec)
0.016
0.032
0.064
0.128
0.256
0.5
1.0
2.0
000
001
010
011
100
101
110
111
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