參數(shù)資料
型號(hào): SX52BD
廠商: Electronic Theatre Controls, Inc.
英文描述: Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability, and On-Chip Debug
中文描述: 配置通信控制器與電子工程/閃存程序存儲(chǔ)器,在系統(tǒng)編程能力,以及片上調(diào)試
文件頁數(shù): 39/58頁
文件大?。?/td> 873K
代理商: SX52BD
2002 Ubicom, Inc. All rights reserved.
- 39 -
www.ubicom.com
SX48BD/SX52BD
A 2-bit field in the FUSEX register can be used to specify
the Delay Reset Timer (DRT) timeout period that results
in an automatic wake-up from the power down mode.
10 = 0.25 msec
11 = 18 msec (default)
00 = 60 msec
01 = 1 sec
For fast start-up from the power down mode, clear the
SLEEPCLK bit and set the WDRT1:WDRT0 field to 00.
This will keep the clock operating during the power down
mode and allow a minimum start-up delay.
Note 1: The external Power-On Reset circuit is required
only if V
dd
power-up is too slow. The diode D helps dis-
charge the capacitor quickly when V
dd
powers down and
comes back within a short period of time.
Note 2: R < 40 k
is recommended to make sure that
voltage drop across R does not violate the device electri-
cal specifications.
R1 = 100
to 1k
will limit any current flowing into MCLR
from external capacitor C. This helps prevent MCLR pin
breakdown due to Electrostatic Discharge (ESD) or Elec-
trical Overstress (EOS).
13.0
The on-chip brown-out detection circuitry resets the
device when V
dd
dips below the specified brown-out volt-
age. The device is held in reset as long as V
dd
stays
below the brown-out voltage. The device will come out of
reset when V
dd
rises above the brown-out voltage. The
brown-out level can be set to 2.2V, 2.4V, OR 4.1V levels
through BOR1:BOR0 bits in the FUSEX register.
BROWN-OUT DETECTOR
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