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參數(shù)資料
| 型號： | SX52BD |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability, and On-Chip Debug |
| 中文描述： | 配置通信控制器與電子工程/閃存程序存儲器，在系統(tǒng)編程能力，以及片上調(diào)試 |
| 文件頁數(shù)： | 32/58頁 |
| 文件大小： | 873K |
| 代理商： | SX52BD |
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2002 Ubicom, Inc. All rights reserved.
- 32 -
www.ubicom.com
SX48BD/SX52BD
Timer T1 Control A Register (T1CNTA)
T1CPF2
7
T1CPF1
6
T1CPIE
5
T1CMF2
4
T1CMF1
3
T1CMIE
2
T1OVF
1
T1OVIE
0
T1CPF2
Timer T1 Capture Flag 2. In Capture/Compare mode, this flag is automatically set to 1 when a capture
event occurs on the Capture 2 pin of Timer T1 (pin RB5). It stays set until cleared by the software.
Timer T1 Capture Flag 1. In Capture/Compare mode, this flag is automatically set to 1 when a capture
event occurs on the Capture 1 pin of Timer T1 (pin RB4). It stays set until cleared by the software.
Timer T1 Capture Interrupt Enable. Set this bit to 1 to enable capture interrupts for Timer T1 in Cap-
ture/Compare mode. In that case, an interrupt will occur each time a valid edge is received on the Cap-
ture 1 or Capture 2 pin of Timer T1. Clear this bit to 0 to disable capture interrupts.
Timer T1 Comparison Flag 2. This flag is automatically set to 1 when the contents of the timer counter
match the contents of R2, when R2 is the active comparison register. The flag stays set until it is
cleared by the software.
Timer T1 Comparison Flag 1. This flag is automatically set to 1 when the contents of the timer counter
match the contents of R1, when R1 is the active comparison register. The flag stays set until it is
cleared by the software.
Timer T1 Comparison Interrupt Enable. Set this bit to 1 to enable comparison interrupts for Timer T1. In
that case, an interrupt will occur each time the contents of the timer counter match the contents of the
active comparison register (R1 or R2) of Timer T1. Clear this bit to 0 to disable comparison interrupts.
Timer T1 Overflow Flag. This flag is automatically set to 1 when the timer counter overflows from
FFFFh to 0000h. The flag stays set until it is cleared by the software.
Timer T1 Overflow Interrupt Enable. Set this bit to 1 to enable overflow interrupts for Timer T1. In that
case, an interrupt will occur each time Timer T1 overflows. Clear this bit to 0 to disable overflow inter-
rupts.
T1CPF1
T1CPIE
T1CMF2
T1CMF1
T1CMIE
T1OVF
T1OVIE
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SX52BD/PQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability, and On-Chip Debug |
| SX52F | 制造商:PANJIT 制造商全稱:Pan Jit International Inc. 功能描述:SCHOTTKY BARRIER RECTIFIER |
| SX52F_R1_00001 | 制造商:PANJIT 制造商全稱:Pan Jit International Inc. 功能描述:SCHOTTKY BARRIER RECTIFIER |
| SX52F_R2_00001 | 制造商:PANJIT 制造商全稱:Pan Jit International Inc. 功能描述:SCHOTTKY BARRIER RECTIFIER |
| SX53F | 制造商:PANJIT 制造商全稱:Pan Jit International Inc. 功能描述:SCHOTTKY BARRIER RECTIFIER |
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