參數(shù)資料
型號: STPCATLAS
廠商: 意法半導(dǎo)體
英文描述: X86 Core PC Compatible System-on-Chip for Terminals
中文描述: x86內(nèi)核PC兼容系統(tǒng)上的終端芯片
文件頁數(shù): 82/111頁
文件大?。?/td> 1896K
代理商: STPCATLAS
DESIGN GUIDELINES
82/111
Issue 1.0 - July 24, 2002
In the case of higher clock load it is recommended
to use a zero-delay clock buffer as described in
Figure 6-9
. This approach is also recommended
Figure 6-9. PCI clock routing with zero-delay clock buffer
when implementing the delay on PCICLKI
according to the PCI section of the
Electrical
Specifications
chapter.
PCICLKI
PCICLKO
Device A
Device B
Device C
PLL
Device D
PCICLKI
PCICLKO
Device A
Device B
Device C
PLL
Device D
CY2305
CY2305
Implementation 1
Implementation 2
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參數(shù)描述
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