參數(shù)資料
型號(hào)： STPCATLAS
廠商： 意法半導(dǎo)體
英文描述： X86 Core PC Compatible System-on-Chip for Terminals
中文描述： x86內(nèi)核PC兼容系統(tǒng)上的終端芯片
文件頁(yè)數(shù)： 38/111頁(yè)
文件大?。?/td> 1896K
代理商： STPCATLAS
STRAP OPTION
38/
111
Issue 1.0
- July 24, 2002
3.1.4. STRAP REGISTER 2
This register is read only with the exception of bit 4
STRAP2
Access = 0022h/0023h
Regoffset =04Ch
7
6
5
4
3
2
1
0
MD[53]
MD[52]
RSV
MD[20]
MD[19]
MD[18]
MD[51]
MD[50]
This register defaults to the values sampled on the MD pins after reset
Bit Number Sampled
Mnemonic
Description
Bit 7
MD[53]
This bit reflects the value sampled on MD[53] pin and determines
whether the internal Parallel Port Controller is used
0: Internal Parallel Port Controller is disabled
1: Internal Parallel Port Controller is enabled
Bit 6
MD[52]
This bit reflects the value sampled on MD[52] pin and determines
whether the internal Keyboard controller is used
0: Internal Keyboard Controller is disabled
1: Internal Keyboard Controller is enabled
Bit 5
Rsv
Reserved
Bit 4
MD[20]
This bit reflects the value sampled on MD[20] pin and controls the Dot
clock pin (DCLK) direction as follows:
0: Input.
1: Output of the internal frequency synthesizer DCLK PLL.
Bit 3
MD[19]
This bit reflects the value sampled on MD[19] pin and controls the
Memory clock output pin (MCLKO) as follows:
0: Tristated.
1: Output of the internal frequency synthesizer MCLKO PLL.
Bit 2
MD[18]
This bit reflects the value sampled on MD[18] pin and controls the Host
clock pin (HCLK) direction as follows:
0: Input.
1: Output of the internal frequency synthesizer HCLK PLL.
Bit 1
MD[51]
This bit reflects the value sampled on MD[51] pin and determines
whether the internal UART1 is enabled:
0: Internal UART1 is disabled
1: Internal UART1 is enabled
Bit 0
MD[50]
This bit reflects the value sampled on MD[50] pin and determines
whether the internal UART2 is enabled:
0: Internal UART2 is disabled
1: Internal UART2 is enabled
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