參數(shù)資料
型號: STPCATLAS
廠商: 意法半導(dǎo)體
英文描述: X86 Core PC Compatible System-on-Chip for Terminals
中文描述: x86內(nèi)核PC兼容系統(tǒng)上的終端芯片
文件頁數(shù): 52/111頁
文件大?。?/td> 1896K
代理商: STPCATLAS
ELECTRICAL SPECIFICATIONS
52/111
Issue 1.0 - July 24, 2002
4.5.4. PCI INTERFACE
Figure 4-6
and
Table 4-12
list the AC characteris-
tics of the PCI interface. PCICLKx stands for any
PCI device clock input.
Figure 4-6. PCI Timing Diagram
PCICLKI
STPC.output
STPC.input
PCICLKx
T
clkx
T
setup
T
hold
T
output (min)
T
output (max)
T
cycle
T
high
T
low
HCLK
T
hclk
Table 4-12. PCI Bus AC Timings
Name
Parameter
HCLK to PCICLKO delay (MD[30:27] = 1111)
HCLK to PCICLKI delay
PCICLKI to PCICLKx skew
PCICLKI Cycle Time
PCICLKI High Time
PCICLKI Low Time
PCICLKI Rising Time
PCICLKI Falling Time
PCICLKI to any output
Setup to PCICLKI
Hold from PCICLKI
HCLK to any output
Setup to HCLK
Hold from HCLK
Note: These timings are for a load of 50pF.
Min
4.4
6.5
-0.5
30
13
13
Typ
5.0
7.5
0.3
Max
5.7
8.5
1.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Thclk
Tclkx
Tcycle
Thigh
Tlow
1.5
1.5
-
-
-
-
-
-
-
-
-
-
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