參數(shù)資料
型號(hào)： STPCATLAS
廠商： 意法半導(dǎo)體
英文描述： X86 Core PC Compatible System-on-Chip for Terminals
中文描述： x86內(nèi)核PC兼容系統(tǒng)上的終端芯片
文件頁(yè)數(shù)： 33/111頁(yè)
文件大?。?/td> 1896K
代理商： STPCATLAS
STRAP OPTION
Issue 1.0
- July 24, 2002
33/
111
3. STRAP OPTION
This chapter defines the STPC Atlas Strap
Options and their locations. Some strap options
are left programmable for future versions of
silicon. The strap options are sampled at a specific
point of the boot process. This is shown in detail in
Figure 4-3
Signal
Designation
Location
Actual
Settings
Pull Up
User defined
User defined
Pull-up
User defined
User defined
Pull-down
User defined
User defined
Pull down
Pull down
Pull-up
Pull up
Pull up
User defined
Pull-up
Pull-up
User defined
Pull up
Pull up
User defined
User defined
User defined
Pull up
Pull up
Pull up
Pull up
Pull up
Pull down
Pull up
Pull down
Pull down
User defined
Pull down
Pull down
User defined
Pull down
Pull up
Pull down
Set to ’0’
Set to ’1’
MD1
MD2
MD3
MD[4]
MD[5]
MD[6]
MD[7]
MD[8]
MD[9]
MD10
MD11
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD40
MD41
MD42
MD 43
Reserved
2
Not accessible
Index 5F,bit 6
Index 5F,bit 7
Index 4A,bit 1
Index 4A,bit 2
Index 4A,bit 6
Index 4A,bit 7
Index 4A,bit 3
Index 4A,bit 3
Index 4B,bit 2
Index 4B,bit 3
Index 4B,bit 6
Not accessible
Not accessible
Index 4A,bit 0
Index 4C,bit 2
Index 4C,bit 3
Index 4C,bit 4
Index 5F,bit 0
Index 5F,bit 2
Index 5F,bit 3
Index 5F,bit 4
Index 5F,bit 5
Not accessible
Not accessible
Not accessible
Not accessible
Not accessible
Not accessible
Not accessible
Not accessible
Not accessible
Index 4B,bit 0
Not accessible
Not accessible
Index 4B,bit 7
Not accessible
Not accessible
Not accessible
-
-
HCLK Speed
See
Section 3.1.3.
PCI_CLKO Divisor
MCLK Synchro (see
Section 3.1.1.
)
See
Section 3.1.1.
Async
Sync
PCI_CLKO Programming
See
Section 3.1.1.
ISA / PCMCIA / Local Bus
See
Section 3.1.1.
Reserved
2
Reserved
2
-
-
-
-
CPU clock Multiplication
Reserved
2
Reserved
2
PCI_CLKO Divisor
HCLK Pad Direction
MCLK Pad Direction
DCLK Pad Direction
Reserved
2
Reserved
2
See
Section 3.1.2.
-
-
See
Section 3.1.1.
Input
Hi-Z
Input
-
-
-
-
Output
Output
Output
-
-
HCLK PLL Speed
See
Section 3.1.3.
Reserved
2
Reserved
2
Reserved
2
Reserved
2
Reserved
2
Reserved
2
Reserved
2
Reserved
2
Reserved
2
-
-
-
-
-
-
-
-
Local Bus Boot Device Size
Reserved
2
Reserved
2
CPU clock Multiplication
Reserved
2
Reserved
2
Reserved
2
8-bit
-
-
See
Section 3.1.2.
-
-
-
16-bit
-
-
-
-
-
Note
1
: Strap options on TC/PA[3] and DACK_ENC[2:0]/PA[2:0] are required for all the STPC Atlas Configurations (ISA,
PCMCIA, Local Bus).
Note
2
: Must be implemented.
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