參數(shù)資料
型號(hào)： STPCATLAS
廠商： 意法半導(dǎo)體
英文描述： X86 Core PC Compatible System-on-Chip for Terminals
中文描述： x86內(nèi)核PC兼容系統(tǒng)上的終端芯片
文件頁(yè)數(shù)： 49/111頁(yè)
文件大?。?/td> 1896K
代理商： STPCATLAS
ELECTRICAL SPECIFICATIONS
Issue 1.0 - July 24, 2002
49/111
4.5.2 RESET SEQUENCE
Figure 4-4
describes the reset sequence of the
STPC, also called warm reset.
The constraints on the strap options and the bus
activities are the same as for the cold reset.
The SYSRSTI# pulse duration must be long
enough to have all the strap options stabilized and
must be adjusted depending on resistor values.
Figure 4-4. Reset timing diagram
It is mandatory to have a clean reset pulse without
glitches as the STPC could then sample invalid
strap option setting and enter into an umpredicta-
ble mode.
While SYSRSTI# is active, the PCI clock PLL runs
in open loop mode at a speed of few 100’s KHz.
Strap Options
SYSRSTI#
SYSRSTO#
14 MHz
VALID CONFIGURATION
HCLK
PCI_CLK
2.3 ms
ISACLK
1.6 V
MD[63:0]
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