參數(shù)資料
型號(hào)： STPC CONSUMER
廠商： 意法半導(dǎo)體
英文描述： Multimedia PC on a Chip(多媒體PC)
中文描述： 多媒體電腦芯片（多媒體個(gè)人電腦）
文件頁(yè)數(shù)： 15/34頁(yè)
文件大?。?/td> 388K
代理商： STPC CONSUMER
PIN DESCRIPTION
15/34
MD[63:0]
Memory Data I/O. This is the 64-bit
memory data bus. If only half of a bank is populat-
ed, MD63-32 is pulled high, data is on MD31-0.
MD[40-0] are read by the device strap option reg-
isters during rising edge of PWGD.
RAS#[3:0]
Row Address Strobe Output. There
are 4 active low row address strobe outputs, one
each for each bank of the memory. Each bank
contains 4 or 8-bytes of data. The memory control-
ler allows half of a bank (4-bytes) to be populated
to enable memory upgrade at finer granularity.
The RAS# signals drive the SIMMs directly with-
out any external buffering. These pins are always
outputs, but they can also simultaneously be in-
puts, to allow the memory controller to monitor the
value of the RAS# signals at the pins.
CAS#[7:0]
Column Address Strobe Output.There
are 8 active low column address strobe outputs,
one each for each byte of the memory.
The CAS# signals drive the SIMMs either directly
or through external buffers.
These pins are always outputs, but they can also
simultaneously be inputs, to allow the memory
controller to monitor the value of the CAS# signals
at the pins.
MWE#
Write Enable Output.Write enable speci-
fies whether the memory access is a read (MWE#
= H) or a write (MWE# = L). This single write ena-
ble controls all DRAMs. It can be externally buff-
ered to boost the maximum number of loads
(DRAM chips) supported.
The MWE# signals drive the SIMMs directly with-
out any external buffering.
2.2.3 VIDEO INTERFACE
VCLK
Pixel Clock Input.
VIN[7:0]
YUV Video Data Input CCIR 601 or 656.
Time multiplexed 4:2:2 luminance and chromi-
nance data as defined in ITU-R Rec601-2 and
Rec656 (except for TTL input levels). This bus in-
terfaces with an MPEG video decoder output port
and typically carries a stream of Cb,Y,Cr,Y digital
video at VCLK frequency, clocked on the rising
edge (by default) of VCLK. A 54-Mbit/s ‘double’
Cb, Y, Cr,Y input multiplex is supported for double
encoding application (rising and falling edge of
CKREF are operating).
2.2.4 TV OUTPUT
RED_TV / C_TV
Analog video outputs synchro-
nized with CVBS.This output is current-driven and
must be connected to analog ground over a load
resistor (R
). Following the load resistor, a
simple analog low pass filter is recommended. In
S-VHS mode, this is the Chrominance Output.
GREEN_TV / Y_TV
Analog video outputs syn-
chronized with CVBS.This output is current-driv-
en and must be connected to analog ground over
a load resistor (R
). Following the load resis-
tor, a simple analog low pass filter is recommend-
ed. In S-VHS mode, this is the Luminance Output.
BLUE_TV / CVBS
Analog video outputs synchro-
nized with CVBS.This output is current-driven and
must be connected to analog ground over a load
resistor (R
LOAD
). Following the load resistor, a
simple analog low pass filter is recommended. In
S-VHS mode, this is a second composite output.
VCS
Line synchronisation Output.This pin is an
input in ODDEV+HSYNC or VSYNC + HSYNC or
VSYNC slave modes and an output in all other
modes (master/slave)
The signal is synchronous to rising edge of CK-
REF. The default polarity uses a negative pulse
ODD_EVEN
Frame Synchronisation Ourput.This
pin supports the Frame synchronisation signal. It
is an input in slave modes, except when sync is
extracted from YCrCbdata, and an output in mas-
ter mode and when sync is extracted from YCrCb
data
The signal is synchronous to rising edge of DCLK.
The default polarity for this pin is:
- odd (not-top) field : LOW level
- even (bottom) field : HIGH level
IREF1_TV
Ref. currentfor CVBS 10-bit DAC.
VREF1_TV
Ref. voltagefor CVBS 10-bit DAC.
IREF2_TV
Reference currentfor RGB 9-bit DAC.
VREF2_TV
Reference voltagefor RGB 9-bit DAC.
VSSA_TV
Analog V
SS
for DAC
VDDA_TV
Analog V
DD
for DAC
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