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參數(shù)資料
| 型號： | STPC CONSUMER |
| 廠商： | 意法半導體 |
| 英文描述： | Multimedia PC on a Chip(多媒體PC) |
| 中文描述： | 多媒體電腦芯片（多媒體個人電腦） |
| 文件頁數(shù)： | 14/34頁 |
| 文件大?。?/td> | 388K |
| 代理商： | STPC CONSUMER |
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PIN DESCRIPTION
14/34
2.2 SIGNAL DESCRIPTIONS
2.2.1 BASIC CLOCKS AND RESETS
PWGD
System Reset/Power good. This input is
low when the the reset switch is depressed. Other-
wise, it reflects the power supply’s power good
signal. PWGD is asynchronous to all clocks, and
acts as a negative active reset. The reset circuit
initiates a hard reset on the rising edge of PWGD.
SYSRSTO#
Reset Output to System.This is the
system reset signal and is used to reset the rest of
the components (not on Host bus) in the system.
The ISA bus reset is an externally inverted buff-
ered version of this output and the PCI bus reset is
an externally buffered version of this output.
XTALI
14.3MHz Crystal Input
XTALO
14.3MHz Crystal Output.These pins are
the 14.318 MHz crystal input; This clock is used as
the reference clock for the internal frequency syn-
thesizer
to
generate
GCLK2X and DCLK clocks.
A 14.318 MHz Series Cut Quartz Crystal should
be connected between these two pins. Balance
capacitors of 15 pF should also be added. In the
event of an external oscillator providing the master
clock signal to the STPC Consumer device, the
TTL signal should be provided on XTALO.
the
HCLK,
CLK24M,
HCLK
Host Clock. This is the host 1X clock. Its
frequency can vary from 25 to 75 MHz. All host
transactions and PCI transactions are synchro-
nized to this clock. The DRAM controller to exe-
cute the host transactions is also driven by this
clock. In normal mode, this output clock is gener-
ated by the internal pll.
GCLK2X
80MHz Graphics Clock. This is the
Graphics 2X clock, which drives the graphics en-
gine and the the DRAM controller to execute the
graphics and display cycles.
Normally GCLK2X is generated by the internal fre-
quency synthesizer, and this pin is an output. By
setting a bit in Strap Register 2, this pin can be
made an input so that an external clock can re-
place the internal frequency synthesizer.
PCI_CLKI
33MHz PCI Input Clock
This signal is the PCI bus clock input and should
be driven from the PCI_CLKO pin.
PCI_CLKO
33MHz PCI Output Clock.This is the
master PCI bus clock output.
DCLK
135MHz Dot Clock. This is the dot clock,
which drives graphics display cycles. Its frequency
can be as high as 135 MHz, and it is required to
have a worst case duty cycle of 60-40.
This signal is either driven by the internal pll (VGA)
either by an external 27MHz oscillator (TV). The
direction can be controlled by a strap option or an
internal register bit.
DISA_CLK
ISA Clock Output (also Multiplexer
Select Line For IPC).This pin produces the Clock
signal for the ISA bus. It is also used with
ISA_CLK2X as the multiplexor control lines for the
Interrupt Controller Interrupt input lines. This is di-
vided down version of either the PCICLK or
OSC14M.
ISA_CLKX2
ISA Clock Output (also Multiplexer
Select Line For IPC).This pin produces a signal at
twice the frequency of the Clock signal for the ISA
bus. It is also used with ISA_CLK as the multiplex-
or control lines for the Interrupt Controller Interrupt
input lines.
DEV_CLK
24MHz Peripheral Clock Output.This
24MHZ signal is provided as a convenience for
the system integration of a Floppy Disk driver
function in an external chip.
OSC14M
ISA bus synchronisation clock Output.
This is the buffered 14.318 Mhz clock to the ISA
bus.
2.2.2 MEMORY INTERFACE
MA[11:0]
Memory Address Output.These 12 mul-
tiplexed memory address pins support external
DRAM with up to 4K refresh. These include all
16M x N and some 4M x N DRAM modules. The
address signals must be externally buffered to
support more than 16 DRAM chips. The timing of
these signals can be adjusted by software to
match the timings of most DRAM modules.
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