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參數(shù)資料
| 型號： | STB4395 |
| 廠商： | 意法半導體 |
| 英文描述： | CT2 Receiver/Transmitter(CT2接收器/發(fā)送器) |
| 中文描述： | 第二代無線電話接收器/發(fā)送器（第二代無線電話接收器/發(fā)送器） |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 153K |
| 代理商： | STB4395 |
3 - FUNCTIONALDESCRIPTION
Figure 1 is a simplified block diagram of the circuit.
It shows the key on-chip and off-chip functional
blocks and signal paths. For illustration purposes
frequencies have been added representing the
situationwhenreceivingortransmittingaparticular
CT2 channel.
3.1 - Receiver
The receivesignalenterstheSTB4395viaaninput
SAW filter (866 MHZ for CT2 in Europe).The RF
filter changes the input signal froma singleended
to a balanced signal,after which thesignal passes
through the LNA, first mixer, and mixer buffer. The
mixeris drivenbythechannelVCO,whichis inturn
controlledby the synthesizer.
The signal path continues via the first IF SAW
(150.4MHz), IF amplifier to the second mixer. The
second mixer stage mixes down to 1.7MHz, and
via an externalLC IF filter, is passed to the second
IF amplifier, where the main system gain takes
place. The RSSI output is available from this
point.The signal is then demodulated and sliced
into adata stream which isthe binarydigital output
availableto the base band chip.
The channelselectionis providedbythetwoexter-
nal filters:the first IF SAW and a secondIF 2-pole
LC filter.
3.2 - Transmitter
The chip accepts 72Kbits/sdata in an I/Q format.
The I/Q inputs pass via the I/Q modulator to the
TX mixer. The TX mixer is driven by the same
channel VCO as the receive first mixer.
The on-offramp ofthetransmit PA.iscontrolledvia
an external capacitor to give minimum spurious
responseswhen switching on and off.
The PA output power can be switched from full
power to -3dBm by
the channel select control
signal (bit LOof the 16bitsserial word PRGD, see
table,paragraph 1.4).
3.3 - Channel SelectControl Logic
All channel phase locked loops and oscillators are
included on chip. The channelcontrol synthesizer
is controlledexternally via a 3 wire interface.
The Reference clock input of 14.4 MHz is divided
using preset counters to set the phase detector
/charge pump loops for the synthesizer/channel
select VCO,the secondreceiver VCO, and the I/Q
transmit VCO. The phase detector inputs for the
fixedfrequency VCO’s areviapreset dividersalso.
The channelselectcontroland TransmitPAcontrol
is viaa 16bit serialword, whichisgeneratedbythe
system controller. 15 bits of this serial word are
used forthe channel information,and 1 bit is used
to settheoutputpowerofthetransmitPA.Theword
length is sufficient to give full channel coverage
over the range from 800 to 1000MHz with integer
multiples of 50KHz. The section ”system clock
input” gives a detaileddescription.
Not shown in the diagram are the voltageregula-
torsforthe receiveLNA/firstmixer, TransmitPA,TX
mixerand the remainder of the circuit.Thereare 6
internal voltageregulators to ensure the minimum
of mutualinterference.
4 - ABSOLUTEMAXIMUM RATINGS
Symbol
V
P
-V
N
V
P
- V
IN
V
P
- V
IN
V
IN
- V
N
V
P
- V
OUT
V
N
- V
OUT
V
RFO
T
stg
T
oper
Parameter
Value
7.0
5.9
3.0
7.0
7.0
7.0
3.5
125
40
Unit
V
V
V
V
V
V
V
PP
o
C
o
C
Power Supply Voltage
Voltages on Input (except SYNCLK)
Voltage on Input (SYNCLK)
Voltages on Input
Voltages on Output
Voltages on Output
Voltage Out of RF or NRF in TX
Storage Temperature
Operating Temperature
STB4395
8/16
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