參數(shù)資料
型號： ST72774S9T1/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP44
封裝： TQFP-44
文件頁數(shù)： 58/144頁
文件大?。?/td> 1280K
代理商： ST72774S9T1/XXX
ST72774/ST727754/ST72734
20/144
3.2 RESET
The Reset procedure is used to provide an orderly
software start-up or to quit low power modes.
Five conditions generate a reset:
s
LVD,
s
watchdog,
s
external pulse at the RESET pin,
s
illegal address,
s
illegal opcode.
A reset causes the reset vector to be fetched from
addresses FFFEh and FFFFh in order to be loaded
into the PC and with program execution starting
from this point.
An internal circuitry provides a 4096 CPU clock
cycle delay from the time that the oscillator
becomes active.
3.2.1 LVD and Watchdog Reset
The Low Voltage Detector (LVD) generates a reset
when VDD is below VTRH when VDD is rising or VTRL
when VDD is falling (refer to Figure 11). This circuitry
is active only when VDD is above VTRM.
During LVD Reset, the RESET pin is held low, thus
permitting the MCU to reset other devices.
When a watchdog reset occurs, the RESET pin is
pulled low permitting the MCU to reset other
devices as when Power on/off (Figure 10).
3.2.2 External Reset
The external reset is an active low input signal
applied to the RESET pin of the MCU.
As shown in Figure 12, the RESET signal must
remain low for 1000ns.
An internal Schmitt trigger at the RESET pin is
provided to improve noise immunity.
3.2.3 Illegal Address Detection
An opcode fetch from an illegal address (refer to
Figure 3) generates an illegal address reset.
Program
execution
at
those
addresses
is
forbidden (especially to protect page 0 registers
against spurious accesses).
3.2.4 Illegal Opcode Detection
Illegal instructions corresponding to no valid
opcode
generate
a
reset.
Refer
to
ST7
Programming Manual.
Table 5. List of sections affected by RESET and WAIT (Refer to 3.6 for Wait Mode)
Section
RESET
WAIT
Fast bit of the miscellaneous register set to one (24 MHz as external clock)
X
Timer Prescaler reset to zero
X
Timer Counter set to FFFCh
X
All Timer enable bits set to 0 (disabled)
X
Data Direction Registers set to 0 (as Inputs)
X
Set Stack Pointer to 01FFh
X
Force Internal Address Bus to restart vector FFFEh, FFFFh
X
Set Interrupt Mask Bit (I-Bit, CC) to 1 (Interrupt disable)
X
Set Interrupt Mask Bit (I-Bit, CC) to 0 (Interrupt enable)
X
Reset WAIT latch
X
Disable Oscillator (for 4096 cycles)
X
Set Timer Clock to 0
X
Watchdog counter reset
X
Watchdog register reset
X
Port data registers reset
X
Other on-chip peripherals: registers reset
X
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