參數(shù)資料
型號(hào)： ST72774S9T1/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP44
封裝： TQFP-44
文件頁數(shù)： 5/144頁
文件大?。?/td> 1280K
代理商： ST72774S9T1/XXX
ST72774/ST727754/ST72734
102/144
DDC INTERFACE (Cont’d)
DDC2B Mode: The DDC1/2B Interface enters
DDC2B mode either from the transition state or
from the initial state if software sets the HWPE bit
while P&D only or FPDI-2 mode is selected.
Once in DDC2B mode, the Interface always acts
as a slave following the protocol described in
Figure 62.
The DDC1/2B Interface continuously monitors the
SDA and SCL lines for a START condition and will
not respond (no acknowledge) until one is found.
A STOP condition at the end of a Read command
(after a NACK) forces the stand-by state. A STOP
condition at the end of a Write command triggers
the internal DMA write cycle.
The Interface samples the SDA line on the rising
edge of SCL and outputs data on the falling edge
of SCL. In any case SDA can only change when
SCL is low.
Figure 62. DDC2B protocol (example)
SDA
SCL
Start
Ack
A0h
Device Slave
00h
Data Address
Ack
Start A1h
Data1
Ack
DataN
Nack
Stop
Address
Device Slave
Address
128 / 256 bytes EDID
Legend:
Italics = data / control signal from display
Ack
Bold = data / control signal from host
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