參數(shù)資料
型號(hào)： ST72774S9T1/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP44
封裝： TQFP-44
文件頁數(shù)： 123/144頁
文件大?。?/td> 1280K
代理商： ST72774S9T1/XXX
ST72774/ST727754/ST72734
8/144
PIN DESCRIPTION (Cont’d)
RESET: Bidirectional. This active low signal forces
the initialization of the MCU. This event is the top
priority non maskable interrupt. This pin is
switched low when the Watchdog has triggered or
VDD is low. It can be used to reset external
peripherals.
OSCIN/OSCOUT:
Input/Output Oscillator
pin.
These pins connect a parallel-resonant crystal, or
an external source to the on-chip oscillator.
TEST/VPP: Input. EPROM programming voltage.
This pin must be held low during normal operating
modes.
VDD: Power supply voltage (4.0V-5.5V)
VSS: Digital Ground.
Alternate Functions: several pins of the I/O ports
assume
software
programmable
alternate
functions as shown in the pin description
Table 1. ST727x4 Pin Description
Pin No.
Pin Name
Type
Description
Remarks
TQ
FP
4
SD
IP
4
2
39
1
PC0/HSYNCDIV
I/O
Port C0 or HSYNCDIV output (HSYNCO divided by 2)
40
2
PC1/AV
I/O
Port C1 or “Active Video” input
41
3
PC2/PWM3
I/O
Port C2 or 10-bit PWM/BRM output 3
For analog controls,
after external filtering
42
4
PC3/PWM4
I/O
Port C3 or 10-bit PWM/BRM output 4
43
5
PC4/PWM5
I/O
Port C4 or 10-bit PWM/BRM output5
44
6
PC5/PWM6
I/O
Port C5 or 10-bit PWM/BRM output 6
1
7
PC6/PWM7
I/O
Port C6 or 10-bit PWM/BRM output 7
2
8
PC7/PWM8
I/O
Port C7 or 10-bit PWM/BRM output 8
3
9
PB7/AIN3/PWM2
I/O
Port B7 or ADC analog input 3 or 10-bit PWM/BRM
output 2
4
10
PB6/AIN2/PWM1
I/O
Port B6 or ADC analog input 2 or 10-bit PWM/BRM
output 1
5
11
PB5/AIN1
I/O
Port B5 or ADC analog input 1
6
12
PB4/AIN0
I/O
Port B4 or ADC analog input 0
813
VDD
S
Supply (4.0V - 5.5V)
9
14
USBVCC
S
USB power supply (output 3.3V +/- 10%)
10
15
USBDM
I/O
USB bidirectional data
Must be tied to ground
for devices without
USB peripheral
11
16
USBDP
I/O
USB bidirectional data
12
17
VSS
S
Ground 0V
13
18
HSYNCI
I
SYNC horizontal synchronisation input
TTL levels
Refer to Figure 16
14
19
VSYNCI
I
SYNC vertical synchronisation input
15
20
PD0/VSYNCO
I/O
Port D0 or SYNC vertical synchronisation output
16
21
PD1/HSYNCO
I/O
Port D1 or SYNC horizontal synchronisation output
17
22
PD2/CSYNCI
I/O
Port D2 or SYNC composite synchronisation input
TTL levels with pull-up
(SYNC input)
3
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