參數(shù)資料
型號(hào)： ST72774S9T1/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP44
封裝： TQFP-44
文件頁(yè)數(shù)： 103/144頁(yè)
文件大?。?/td> 1280K
代理商： ST72774S9T1/XXX
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)當(dāng)前第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)
ST72774/ST727754/ST72734
61/144
SYNC PROCESSOR (SYNC) (Cont’d)
4.4.6 Input Processing
4.4.6.1 Detecting Signal Presence
The Sync Processor provides two ways of
checking input signal presence, by directly polling
the LATR Latch Register or using the Timer
interrupts.
Polling check
Use the Latch Register (LATR), to detect the
presence
of
HSYNCI,
VSYNCI,
CSYNCI,
HFBACK and VFBACK signals. These latched bits
are set when the falling edge of the corresponding
signal is detected. They are cleared by software.
Interrupts check
Due to the fact that VSYNCI is connected to Timer
Input Capture 1 and HSYNCI or CSYNCI is
connected to Timer Input Capture 2, the Timer
interrupts can be used to detect the presence of
input signals. Refer to the 16-bit Timer chapter for
the description of the Timer registers.
To use the interrupt method:
– Select Input Capture1 edge detection:
IEDG1 bit in the Timer CR1 register
– Select Input Capture 2 edge detection (must be
falling edge):
IEDG2 bit = 0 in the Timer CR2 register
– Enable Timer Input Capture interrupts:
ICIE bit in the Timer CR1 register.
– Select the Hsync and Vsync input signals:
HVSEL bit in the POLR register
– Enable the prescaler for HSYNCI or CSYNCI
signal:
PSCD bit in the CCR register.
– Select the normal mode:
LCV1/LCV0 bits in the CCR register.
Perform any of the following:
– Check for VSYNCI presence by monitoring inter-
rupt requests from Timer ICAP1. When VSYNCI
is detected then either detect the VSYNCI polar-
ity or check for HSYNCI presence.
– Check for HSYNCI presence by monitoring inter-
rupt requests from Timer ICAP2. On detecting
HSYNCI, either detect its polarity or check if the-
composite sync on HSYNCI pin is detected or
check for CSYNCI presence.
– Check for CSYNCI presence by monitoring inter-
rupt requests from Timer ICAP2.
4.4.6.2 Measuring Sync Period
To measure the sync period, the Sync processor
block uses the Timer Input Capture interrupts:
– ICAP1 connected to VSYNCI signal
– ICAP2 connected to HSYNCI/CSYNCI signal
with a 256 prescaler
Calculating
the
difference
between
two
subsequent Input Captures (16-bit value) gives the
period for 256xPH (horizontal period) and PV
(vertical period).
The period accuracy is one timer clock (500ns at 2
MHz), so that the tolerance is 500ns for PH and
256 * PH (PH accuracy =1.95ns).
Notes:
1) In case of composite sync, the HSYNCI period
measurement can be synchronized on the
VSYNCI pulse by setting and resetting the
prescaler PSCD bit in the CCR register (for this
function, the ICAP2 detection must be selected
as falling edge).
This avoids errors in the period measurement
due to the Vsync pulse.
2) The Timer Interrupt request should be masked
during a write access to any of the Sync
processor control registers.
Important Note:
Since the recognition of the video mode relies
on the accuracy of the measurements, it is
highly recommended to implement a counter-
style
algorithm
which
performs
several
consecutive measurements before switching
between modes.
The purpose of this algorithm is to filter out any
glitches occurring on the video signals.
相關(guān)PDF資料
PDF描述
ST72E734J6D0 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP42
ST72T774S9T1 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP44
ST7294C6B6 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDIP28
ST72T94C6M6 8-BIT, OTPROM, MICROCONTROLLER, PDSO28
ST72C171K2B6 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP32
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST727X4-EMU2B 制造商:STMicroelectronics 功能描述:REALTIME EMULATOR BOARD - Bulk
ST727X4-EPB/US 制造商:STMicroelectronics 功能描述:PROGRAMMER - Bulk
ST-7-28 功能描述:XFRMR PWR 115V 14VAC 2.6A RoHS:是 類別:變壓器 >> 功率 系列:ST 標(biāo)準(zhǔn)包裝:1 系列:260 類型:標(biāo)準(zhǔn) 最大功率:65 VA 主線圈:雙 副線圈:三路，中心抽頭 在某電流時(shí)的串聯(lián)輸出電壓:500 VAC @ 85mA，5 VAC @ 2A，6.3 VAC @ 2A 在某電流時(shí)的并聯(lián)輸出電壓:- 安裝類型:底座安裝 尺寸/尺寸:102.36mm L x 67.31mm W 高度 - 座高（最大）:66.80mm 端接類型:導(dǎo)線引線
ST7-28 制造商:SUPERWORLD 制造商全稱:Superworld Electronics 功能描述:POWER TRANSFORMER
ST7-28B56 功能描述:電源變壓器 SPLIT BOBBIN HORZ MOUNT XFMR RoHS:否 制造商:Triad Magnetics 功率額定值:12 VA 初級(jí)電壓額定值:115 V / 230 V 次級(jí)電壓額定值:12 V / 24 V 安裝風(fēng)格:SMD/SMT 一次繞組:Dual Primary Winding 二次繞組:Dual Secondary Winding 長(zhǎng)度:2.5 in 寬度:2 in 高度:1.062 in
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*