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參數(shù)資料
| 型號： | ST7267C8T1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, LEAD FREE, TQFP-48 |
| 文件頁數(shù)： | 63/189頁 |
| 文件大?。?/td> | 1643K |
| 代理商： | ST7267C8T1/XXX |
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ST7267C8 ST7267R8
155/189
MSCI PARALLEL INTERFACE (Cont’d)
PARALLEL INTERFACE CONFIGURATION REGISTER 1 (PCR1)
Read / Write
Reset Value: 0000 0000 0111 1111 (007Fh)
Bit 15 = START Start communication.(write only)
This bit is set by software and is always read as 0.
Setting in this bit generates a start pulse that initi-
ates the data transfer. In input mode communica-
tion starts immediately (FIFO must be empty). In
output mode communication starts as soon as the
FIFO is full and copied into the buffer.
Important note: When using the PID bit of the
PCR2 register in the MSCI software, a reset of the
PID bit and the setting of the START bit must be
separated by a delay of at least 3 cycles. The use
of 3 additional single-cycle instructions following
the reset can be used for this purpose.
Bit 14:10 = Reserved.
Bit 9:8 = DM[1:0] Data Mode.
These bits are set and cleared by software.
When 8-bit output mode is used, data bytes are
sent to port P1[7:0] or P1[15:8] depending on
whether the LSB or MSB mode is selected. In 16-
bit mode, data is sent to P1[15:0]. When 8-bit
mode is used, the most significant byte is sent or
read first. The FSB bit in the PCR2 register can be
used to reverse byte order when writing into the
FIFO or reading from the FIFO (equivalent to
sending or reading least significant byte first).
00: 8-bit mode on LSB only
01: 8-bit mode on MSB only
10: 16-bit mode.
Bit 7 = DIR Direction.
This bit is set and cleared by software.
In output mode the data ports used are forced to
output mode by the parallel interface when data is
to be output. In input mode the data ports can be
controlled by the MSCI I/O controller registers.
Data ports must be left in input mode so they can
be driven by external device.
0: Input mode
1: Output mode
Bit 6:4 = F[2:0] Frequency prescaler.
These bits are set and cleared by software. They
select the prescaler factor for the control signal
(applied to the 60 MHz clock)
Bit 3 = CP Clock Polarity.
This bit is set and cleared by software.
0: Falling edge clock pulse
1: Rising edge clock pulse
Bit 2:0 = CSS[2:0] Control Signal Shape.
These bits are set and cleared by software.
They are used to select the clock edge position in
the clock cycle by steps of 16.66ns and thus, con-
trol the clock duty cycle. CSS[2:0] must be lower
than F[2:0] or equal to F (Frequency selection) and
greater than 0.
For more detailed description of the control
signal generation refer to chapter "CONFIGURA-
TION OF THE CONTROL LINE SIGNALS"
15
8
7
0
START
-
DM1
DM0
DIR
F2
F1
F0
CP
CSS2
CSS1
CSS0
F[2] F[1] F[0] Control Signal Frequency
0
Not allowed
001
30MHz
010
20MHz
011
15MHz
100
12MHz
101
10MHz
1
0
8.5MHz
1
7.5MHz
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