參數(shù)資料
型號(hào)： ST7267C8T1/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP48
封裝： 7 X 7 MM, LEAD FREE, TQFP-48
文件頁(yè)數(shù)： 20/189頁(yè)
文件大?。?/td> 1643K
代理商： ST7267C8T1/XXX
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ST7267C8 ST7267R8
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MSCI ST7 INTERFACE (Cont’d)
14.2.2 Interrupt generation from MSCI to ST7
Each time the MSCI core executes a STOP in-
struction it stops itself and the STOP bit in the
MSR (MSCI Status Register) is set.
An interrupt is generated if the STPIE bit in the
MCR (MSCI Control Register) is set.
This feature allows the MSCI core to interrupt the
ST7 each time it completes a function ended by a
STOP instruction.
The ITR MSCI CPU instruction sets the ITR bit in
the MSR register without stopping the MSCI cpu.
An interrupt is generated if the STPIE bit in the
MCR (MSCI Control Register) is set.
14.2.3 Program RAM upload
The MSCI ST7 interface provides read and write
access to the program memory of the MSCI core.
The RAM is mapped in the memory array of the
ST7 core like any other memory but access to this
memory is protected depending on the state of the
MSCI system.
To access the memory with the ST7 the MSCI sys-
tem must be in PC or Soft reset, i.e the PCR or
SFTR bits of the MCR (MSCI Control Register) are
set.
In this state, the RAMLD bit of the MCR (MSCI
Control Register) can be set to switch the Data
RAM access from the MSCI to the ST7.
When the RAMLD bit in the MCR (MSCI Control
Register) is reset, the ST7 cannot access the
MSCI program memory:
– a write access by the ST7 to the MSCI program
memory has no effect.
– a read access by the ST7 to the MSCI program
memory returns $00 value.
When the RAMLD bit in the MCR (MSCI Control
Register) is set, the ST7 can read or write from/
into this memory. Reading can be performed ran-
domly at any address of the RAM.
Writing into this memory can only be performed by
writing pairs of bytes starting with the even ad-
dress byte followed by the next higher byte.
Figure 49. Typical ST7 flow for MSCI program memory update
store value in program
at address 2n
store value in program
memory at address 2n+1
memory
plugin code loaded
in MSCI program
memory
?
NO
YES
n<=n+2
Set RAMLD flag by
by writing to MCR
Reset RAMLD flag by
writing to MCR
ST7 core can control
MSCI program
Memory
partial update of
16-bit memory word
with incorrect value
Update of 16-bit
memory word with
correct value
ST7 core can no longer
control the MSCI
program memory
force SFTR or PCR on MSCI
by writing to MCR
MSCI core stopped
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