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參數(shù)資料
| 型號(hào)： | ST7267C8T1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, LEAD FREE, TQFP-48 |
| 文件頁(yè)數(shù)： | 183/189頁(yè) |
| 文件大?。?/td> | 1643K |
| 代理商： | ST7267C8T1/XXX |
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ST7267C8 ST7267R8
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10.5 USB INTERFACE
10.5.1 Introduction
The USB Interface implements a high/full speed
function interface between the USB and the ST7
microcontroller. It is a highly integrated circuit
which includes the transceiver, USB controller and
USB Data Buffer interface. No external compo-
nents are needed apart from the external refer-
ence resistor.
This USB function is based on ST PHY and Men-
tor MUSBHSFC USB2.0 Function controller. So
parts of this specification are based on Mentor
Graphics design documentation and used by per-
mission.
10.5.2 Main Features
■ USB Specification Version 2.0 Compliant
■ On-Chip USB PHY
■ Supports High/Full Speed USB Protocol
■ 1 control endpoint with two 64 byte buffers
■ 1 IN bulk / interrupt endpoint with 64 byte buffers
■ 1 OUT bulk / interrupt endpoint with 64 byte
buffers
■ 1 IN bulk endpoint with a double packet
buffering capability (2*512 bytes)
■ 1 OUT bulk endpoint with a double packet
buffering capability (2*512 bytes)
■ Specific data transfer mode between USB
buffer and MSCI for high transfer rate (does not
require ST7 intervention)
■ USB Suspend/Resume operations
10.5.3 Functional Description
The block diagram in Figure 44, gives an overview
of the USB interface hardware.
For general information on the USB, refer to the
“Universal Serial Bus Specifications” document
available at http://www.usb.org.
USB2.0 PHY
The USB2.0 PHY serialises or deserialises the
USB data in order to send them in parallel (16-bit)
to the USB packet encoding/decoding block.
Packet Encoding/Decoding CRC
This block Encodes/Decodes the packet to be
sent/to be received through the UTMI interface.
It also performs frame formatting, including CRC
generation and checking.
Endpoint Control
This block is composed of two controller state ma-
chines one for endpoint 0 and another for end-
points 1 and 2.
CPU interface
The CPU interface provides the access to the con-
trol and status registers and the USB buffers
(FIFO) for each endpoint (through RAM controller
block). It also generates an interrupt at the end of a
reception / transmission or when suspend or
resume is detected. The CPU interface is compat-
ible with the VSIA standard BVCI (Basic Virtual
Component Interface).
RAM controller
The RAM controller generates the SRAM control
signals to access the endpoint FIFOs selected by
the Endpoint Control block pointer information.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST72681/R12 | 制造商:STMicroelectronics 功能描述:CONTROLLER FOR HIGH-PERFORMANCE BUS-POWERED USB 2.0 FLASH DR - Trays |
| ST72681/S13 | 制造商:STMicroelectronics 功能描述:CONTROLLER FOR HIGH-PERFORMANCE - Trays |
| ST7271 | 制造商:Panasonic Industrial Company 功能描述:IC |
| ST7271N5B1-CLF | 制造商:STMicroelectronics 功能描述: |
| ST727X4-EMU2B | 制造商:STMicroelectronics 功能描述:REALTIME EMULATOR BOARD - Bulk |
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