參數(shù)資料
型號: ST72124J2T
廠商: 意法半導體
英文描述: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
中文描述: 8位單電壓閃存,ADC和16位定時器,SPI和脊髓損傷界面微控制器
文件頁數(shù): 61/153頁
文件大?。?/td> 1533K
代理商: ST72124J2T
ST72334J/N, ST72314J/N, ST72124J
61/153
16-BIT TIMER
(Cont’d)
Notes:
1. After a processor write cycle to the OCiHR reg-
ister, the output compare function is inhibited
until the OCiLR register is also written.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is f
CPU
/2, OCFiand
OCMPi are set while the counter value equals
the OCiR register value (see
Figure 38 on page
62
). This behaviour is the same in OPM or
PWM mode.
When the timer clock is f
CPU
/4, f
CPU
/8 or in
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see
Figure 39 on page 62
).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OC
i
R register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Forced Compare Output capability
When the FOLVibit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVibit has to
be toggled in order to toggle the OCMPipin when
it is enabled (OCiE bit=1). The OCFibit is then not
set by hardware, and thus no interrupt request is
generated.
FOLVLibits have no effect in either One-Pulse
mode or PWM mode.
Figure 37. Output Compare Block Diagram
OUTPUT COMPARE
CIRCUIT
16-bit
OC1R
Register
16 BIT
FREE RUNNING
COUNTER
OC1E
CC0
CC1
OC2E
OLVL1
OLVL2
OCIE
(Control Register 1)
CR1
(Control Register 2)
CR2
0
0
0
OCF2
OCF1
(Status Register)
SR
16-bit
16-bit
OCMP1
Pin
OCMP2
Pin
Latch
1
Latch
2
OC2R
Register
FOLV2 FOLV1
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